Intersil Americas Inc.

Symantec Corporation

Genesis Microchip Corporation

Other

Veritas Technologies LLC

Sage, Inc.

Sandeep Agarwal

Xiaole Chen

Arun Johary

Jayant Vivrekar

Gustavo James Mehas

Karthik Ramamurthy

Zaki Moussaoui

Chio Fai Aglaia Kong

Vrijendra Gokhale

Alok Ashok Sontakke

Manjiri Chitale

A multi-source energy storage system (ESS) includes a master controller and a plurality of ESSs. A first ESS includes an ESS controller and a plurality of micro-ESSs. A first micro-ESS includes a plurality of nano-ESSs, a micro-ESS controller, and a pulse width modulator. A first nano-ESS includes a plurality of cells, a plurality of cell balancing converters, a bidirectional DC-DC converter and a nano-ESS controller. The multi-source ESS operates in a charging mode and a discharging mode. The multi-source ESS is connected to one of a load, an electric grid or a micro-grid, and provides power thereto when it operates in the discharging mode. The multi-source ESS receives power when it operates in the charging mode.

Smart energy storage system

Systems and methods are provided to track cluster nodes and provide high availability in a computing system. A computer system includes hosts, a cluster manager, and a cluster database. The cluster database includes entries corresponding to the hosts which identify the physical location of a corresponding host. The cluster manager uses the data to select at least two hosts and assign the selected hosts to a service group for executing an application. The cluster manager selects hosts via an algorithm that determines which hosts are least likely to share a single point of failure. The data includes a hierarchical group of location attributes describing two or more of a host's country, state, city, building, room, enclosure, and radio frequency identifier (RFID). The location-based algorithm identifies a group of selected hosts whose smallest shared location attribute is highest in the hierarchical group. The system updates the data whenever a physical location of a host changes.

Using location tracking of cluster nodes to avoid single points of failure

A method and apparatus for providing high availability to service groups within a datacenter is described. In one embodiment, the method includes accessing policy master information regarding a plurality of nodes to identify at least one suitable node of the plurality of nodes for operating a service group, generating network topology information to identify at least one single point of failure amongst the plurality of nodes, processing high availability information regarding at least one computer resource at the at least one suitable node and determining availability indicia of the service group based upon the network topology information and the high availability information.

Method and apparatus for providing high availabilty to service groups within a datacenter

A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.

Method for using digital PLL in a voltage regulator

A computer-implemented method for resolving split-brain scenarios in computer clusters may include (1) identifying a plurality of nodes within a computer cluster that are configured to collectively perform at least one task, (2) receiving, from a node within the computer cluster, a failure notification that identifies a link-based communication failure experienced by the node that prevents the nodes within the computer cluster from collectively performing the task, and, upon receiving the failure notification, (3) immediately prompting each node within the computer cluster to participate in an arbitration event in order to identify a subset of the nodes that is to assume responsibility for performing the task subsequent to the link-based communication failure. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for resolving split-brain scenarios in computer clusters

An embodiment of a hysteretic power-supply controller includes a signal generator, frequency adjuster, and signal combiner. The signal generator is operable to generate a switching signal having a first level in response to a control signal being greater than a first reference value and having a second level in response to the control signal being less than a second reference value, the switching signal having an actual frequency and being operable to drive a switching stage that generates a regulated output signal. The frequency adjuster is operable to generate a frequency-adjust signal that is related to a difference between the actual frequency and a desired frequency. And the signal combiner is operable to generate the control signal from the frequency-adjust signal and the regulated output signal. Such a hysteretic power-supply controller may allow one to set the switching frequency to a desired value independently of the parameters of the power supply.

Hysteretic power-supply controller with adjustable switching frequency, and related power supply, system, and method

Circuits, methods, and apparatus for adjusting an NCO output in order to provide a signal that is phase-locked to a reference signal. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to reduce the chance of metastability. During the first, the output of the NCO is phase shifted to the closest correct portion of a cycle of a clock signal. A second correction is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.

Phase error correction circuit for a high speed frequency synthesizer

Circuits, methods, and apparatus for reducing the phase error in an NCO clock output to reduce the clock jitter. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to obtain a substantially glitch-free, high-speed operation. During the first step, the output of the NCO is phase shifted to the closest quarter portion of a cycle of a clock signal. A second correction step is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.

Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency an optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from exsisting methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display

A method and system for scaling an image in accordance with the present invention is disclosed. The method utilizes a plurality of interpolators operating in parallel. Each interpolator operates with a different spatial offset with respect to the other. The final output is the average the output of each interpolator. Normally the initial value of the horizontal and vertical DDA's is zero. Offset is introduced by introducing an initial value in the DDA. Offset has the physical effect of manipulating the weights required for the averaging process in interpolation. Horizontal offset is the initial value in the Horizontal DDA while the vertical offset is the initial value in the Vertical DDA. The present invention relates to implementation in a semiconductor integrated circuit but the concepts can be used in software based image resizing (scaling) algorithms too.

Method and system for dual spatial or temporal scaling

Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

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Fremont, CA, United States of America

Sandeep Agarwal