Kabushiki Kaisha Toshiba

Sanae Ito

Takashi Izumida

Takahisa Kanemura

Hideaki Aochi

Masaru Kito

Ryota Katsumata

Nobutoshi Aoki

Masaki Kondo

Riichiro Shirota

Masaru Kidoh

Akihiro Nitayama

Toshiyuki Enda

Hiroyoshi Tanimoto

Naoki Kusunoki

Hirotaka Amakawa

Yuki Sekino

According to one embodiment, a method of simulating a manufacturing process of a structure including adjacent components, the method includes causing a computer to perform operations of: importing mesh and material data set for each component; specifying, as a calculation target, a region in a first component in which impurities are to be diffused among the components; setting a virtual film of a desired thickness in contact with the region whose material is the same as that of a second component in contact with the specified calculation target; setting boundary conditions at interface between the region and the virtual film, based on the material data; incorporating the boundary conditions into diffusion equations to solve the diffusion equations of the region and the virtual film; and bringing data on the concentration of impurities of the region obtained by the calculation into data on the structure before the specification of the region.

Method and a non-transitory computer-readable recording medium for simulating a manufacturing process of a structure

A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Semiconductor manufacturing method and semiconductor device

A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

Nonvolatile semiconductor memory device

The group creation part divides n ion particles into groups of a group G, a group G, . . . , and a group G. The individual area setting part sets an initial condition calculation area, as an individual area of the group G, and makes the calculation part calculate movement of the ion particle. Then, one by one, the individual area setting part sets an individual area of a group G, based on a range Rp, a dispersion &#x3c3;L, etc. indicating a calculation result of an ion particle belonging to the group G. Further, the individual area setting part implants an ion particle belonging to the group Ginto the individual area of the group Gand makes the calculation part calculate movement of the implanted ion particle.

Ion implantation simulation apparatus, method, and program

A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel region, each of the projected epitaxial silicon regions having a triangular ridge portion, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film.

Semiconductor device

An aspect of the present invention provides a method of carrying out a simulation with simulation data, including, determining whether or not the simulation data includes boundary conditions set for a boundary of a calculation area set for the simulation, computing the influence of the boundary conditions on the inside of the calculation area if the simulation data includes the boundary conditions, displaying the influence of the boundary conditions on the inside of the calculation area, prompting to enter an instruction whether or not the boundary conditions are changed, and if an instruction to make no change in the boundary conditions is entered, carrying out the simulation with the simulation data.

Growing community of inventors

Yokohama, Japan

Sanae Ito