Sandisk 3d LLC

Vlsi Technology, Inc.

Lsi Logic Corporation

Other

Koninklijke Philips Corporation N.v.

Matrix Semiconductor, Inc.

Samuel Vance Dunton

Usha Raghuram

Christopher John Petti

Steven J Radigan

Michael Konevecki

Milind Ganesh Weling

Ronald J Nagahara

Jayanthi Pallinti

Yizhi Xiong

James Montague Cleeves

Calvin T Gabriel

S Brad Herner

Subhas Bothra

Yung-Tin Chen

Michael A Vyvoda

Rao Venkateswara Annapragada

Calvin K Li

Ming-Yi Lee

Liming Zhang

Ron J Nagahara

Pepito Galvez

Dimitrios Dimitrelis

A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.

Methods for protecting patterned features during trench etch

A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

Method for reducing dielectric overetch using a dielectric etch stop at a planar surface

A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.

Conductive hard mask to protect patterned features during trench etch

A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

A method for etching to form a planarized surface is disclosed. Spaced-apart features are formed of a first material, the first material either conductive or insulating. A second material is deposited over and between the first material. The second material is either insulating or conductive, opposite the conductivity of the first material. The second material is preferably self-planarizing during deposition. An unpatterned etch is performed to etch the second material and expose the top of the buried features of the first material. The etch is preferably a two-stage etch: The first stage is selective to the second material. When the second material is exposed, the etch chemistry is changed such that the etch is nonselective, etching the first material and the second material at substantially the same rate until the buried features are exposed across the wafer, producing a substantially planar surface.

Nonselective unpatterned etchback to expose buried patterned features

A method is provided to clean slurry particles from a surface in which tungsten and dielectric are coexposed after a dielectric CMP step. Such a surface is formed when tungsten features are patterned and etched, the tungsten features are covered with dielectric, and the dielectric is planarized to expose tops of the tungsten features. The surface to be cleaned is subjected to mechanical action in an acid environment. Suitable mechanical action includes performing a brief tungsten CMP step on the tungsten features or scrubbing the surface using, for example, a commercial post-CMP scrubber.

Method for cleaning slurry particles from a surface polished by chemical mechanical polishing

In the present invention a dummy structure is formed in a first deposited layer in order to create topography, generally a raised area, in a deposited layer formed above and later than the first deposited layer. This topography may be advantageous in later steps. In one embodiment, transferred topography allows an alignment or overlay mark obscured by an opaque layer to be located by this enhanced topography. In another embodiment, a raised volume of dielectric material prevents features at the outside of an array area from being overpolished during a CMP step. This method may prove useful in other contexts as well. The size, shape, and placement of the dummy structure is tailored to form the desired excess volume.

Method to form topography in a deposited layer above a substrate

When chemical mechanical planarization (CMP) is used to planarize a surface coexposing patterned features and dielectric fill, where patterned features and the fill are formed of materials having very different CMP removal rates or characteristics, the planarized surface may have excessively rough, dishing or recessing may take place, or one or more or the materials may be damaged. In structures in which planarity is important, these problems can be prevented by forming a capping layer on the patterned features, wherein the CMP removal rate of the material forming the capping layer is similar to the CMP removal rate of the dielectric fill.

Method to minimize formation of recess at surface planarized by chemical mechanical planarization

A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material. The eroded portion of the metallic element is thereby restored. By removing precursor material from those areas in which no replacement with the desired material is wanted, the desired material is selectively deposited only in those place where the precursor material remains, and where it is desired to fill in the cavities or dishing that was created in the areas of the softer metallic elements between the harder laterally surrounding elements during a prior chemical mechanical polishing process. Thus, the microelectronic device is more fully planarized, as the dishing is filled in, and the metallic element is supplemented with an additional amount of desired material.

Metal planarization system

A method of testing the processing of a wafer on a CMP apparatus includes processing a control wafer with the CMP apparatus with a predetermined control consumable combination under a predetermined set of control conditions and generating a control data set which describes the processing of the control wafer with the CMP apparatus, the control data set being based upon the control conditions and a removable rate of the control wafer. The method further includes processing a test wafer with a CMP apparatus with a test consumable combination substantially the same as the control consumable combination under a set of test conditions substantially the same as the set of control conditions. The method further includes generating a test data set which describes the processing of the test wafer with the CMP apparatus. The method also includes comparing the test data set with the control data set so as to determine whether the test data set is the same or within a predetermined tolerance range of the control data set.

Method of testing the processing of a semiconductor wafer on a CMP apparatus

Wafers of the present invention comprise a semiconductor layer and a dielectric layer. The semiconductor layer is patterned to form semiconductor regions, and the dielectric layer is deposited on top of the semiconductor layer. Chemical mechanical planarization (CMP) is performed to remove a portion of the dielectric layer, exposing the upper surfaces of the semiconductor regions. The amount of CMP necessary to expose all of the semiconductor regions on the wafer is reduced, because the dielectric is targeted to deposit up to the upper edge of the semiconductor regions in the spaces in between the semiconductor regions. This technique reduces non-uniformities in the thickness of the dielectric and semiconductor layers across the wafer. The thickness of the dielectric or semiconductor layer deposited on polish monitor pads located at the edges of each die may be monitored to determine when enough CMP has been performed to expose each of the semiconductor regions.

Structure and method for wafer comprising dielectric and semiconductor

A multi-platen chemical-mechanical polishing system is used to polish a wafer. The wafer is polished at a first station. During polishing, an endpoint is detected. The endpoint is detected by generating optical radiation by a first light source. The first optical radiation travels through a translucent area in a surface of a first platen and travels through a first polishing pad. After being reflected by the wafer, the optical radiation returns through the first polishing pad through the translucent window to a first optical radiation detector. The first polishing pad has a uniform surface in that no part of the surface of the first polishing pad includes transparent material through which non-scattered optical radiation originating from the first light source can pass and be detected by the first optical radiation detector. Optical radiation that travels through the first polishing pad and is detected by the first optical radiation detector is haze scattered by inclusions within the first polishing pad. Non-scattered light is absorbed by the first polishing pad. The wafer is also polished at a second station. During polishing a final endpoint is detected. The final endpoint is detected by generating optical radiation by a second light source. The second optical radiation travels through a translucent area in a surface of a second platen and travels through a window embedded in a second polishing pad. After being reflected by the wafer, the optical radiation returns through the window embedded in the second polishing pad, through the translucent area in the surface of the second platen, to a second optical radiation detector.

Laser interferometry endpoint detection with windowless polishing pad for chemical mechanical polishing process

A method for planarizing an integrated circuit. The integrated circuit is to be planarized to an upper surface using chemical mechanical polishing. The upper surface of the integrated circuit includes regions of a first material and regions of a second material. The first material has a first polishing rate and desired chemical, physical, and electrical properties. The second material has a second polishing rate and desired chemical, physical, and electrical properties. The first polishing rate is greater than the second polishing rate. The regions of the first material adjoin the regions of the second material at interfaces. The upper surface of the integrated circuit is overlaid with a top layer of the second material, that is to be removed by the chemical mechanical polishing. Both the regions of the second material and the top layer of the second material are deposited during a deposition. The upper surface of the integrated circuit tends to form deleterious tapers at the interfaces between the first material and the second material when the chemical mechanical polishing is taken past a desired end point. The improvement comprises modifying the second material to increase the second polishing rate by adding a dopant to the second material prior to planarizing the integrated circuit. The dopant does not significantly adversely affect either the desired chemical, physical, and electrical properties of the second material, or the desired chemical, physical, and electrical properties of the first material. Thus, by modifying the second polishing rate of the second material, the difference in polishing rates between the first material and the second material is reduced, and the deleterious tapers in the top surface, which are caused at least in part by over polishing a surface that has regions of different materials that have different polishing rates, tend to be eliminated or dramatically reduced, depending at least in part upon how closely the second polishing rate is matched to the first polishing rate by the modification of the second material.

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San Jose, CA, United States of America

Samuel Vance Dunton