International Business Machines Corporation

Other

Advanced Micro Devices Corporation

Globalfoundries Inc.

Sampath Purushothaman

Satyanarayana Venkata Nitta

Matthew Earl Colburn

Roy Rongqing Yu

Elbert Emin Huang

Timothy Joseph Dalton

Stephen McConnell Gates

Jeffrey Curtis Hedrick

Sung Kwon Kang

Jane M Shaw

George Frederick Walker

Katherine Lynn Saenger

Muthumanickam Sankarapandian

Bruce Kenneth Furman

Alessandro Cesare Callegari

Alfred Viehbeck

Christopher Vincent Jahnes

Christos Dimitrios Dimitrakopoulos

Chandrasekhar Narayan

Willi Volksen

Anna Wanda Topol

Kuan-Neng Chen

Daniel C Edelstein

Mukta G Farooq

Alfred Grill

Subramanian Srikanteswara Iyer

Marie Angelopoulos

John Anthony Fitzsimmons

Steven John Koester

Robert Dennis Miller

Kevin Shawn Petrarca

Terry Allen Spooner

Qinghuang Lin

Deborah A Neumayer

David Lee Rath

Terrence Robert O'Toole

Lawrence Alfred Clevenger

Anthony K Stamper

Jeffrey P Gambino

Carl John Radens

Evan G Colgan

Fei Liu

Andrew Herbert Simon

Fuad Elias Doany

Thomas M Shaw

Vincent James McGahay

Dennis Merton Newns

Edward Crandal Cooney, Iii

Carlos Juan Sambucetti

Kenneth Parker Rodbell

Richard Paul Volant

John Christopher Arnold

Eric D Perfecto

Teddie Peregrino Magbitang

Ghavam G Shahidi

James L Hedrick

Voya Rista Markovich

Ratnam Sooriyakumaran

Jeffrey Donald Gelorme

Robert David Allen

Hosadurga K Shobha

Stephen Victor Kosonocky

Shyng-Tsong Chen

Phillip Joe Brock

James L Speidell

Charles Thomas Black

Cornelia K Tsang

Bruce Bennett Doris

Michael Patrick Chudzik

Paul Andrew Moskowitz

Eugene John O'Sullivan

Wu-Song S Huang

Dirk Pfeiffer

Robert H Dennard

Griselda Bonilla

Xiao Hu Liu

Conal Eugene Murray

Rajarao Jammy

Donald Francis Canaperi

Stephen L Buchwalter

Naftali Eliahu Lustig

Stephen Edward Greco

Harold John Hovel

Vishnubhai Vitthalbhai Patel

Michael John Brady

Mahadevaiyer Krishnan

Rama Divakaruni

Chih-Chao Yang

Chung H Lam

Theodorus E Standaert

Hariklia Deligianni

Paul Stephen Andry

Chandrasekharan Kothandaraman

Supratik Guha

Konstantinos I Papathomas

Robert L Wisnieff

Paul Charles Jamison

Robert L Bruce

Kostas I Papathomas

Christopher Bruce Murray

The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Enhanced adhesive materials and processes for 3D applications

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

3D integration method using SOI substrates and structures produced thereby

An article of manufacture is formed by preparing a first silicon-on-insulator (SOI) wafer with first bonding pads at a first top or back-end-of-line (BEOL) surface thereof, preparing a second SOI wafer with second bonding pads at a second BEOL surface thereof, and attaching the first and second SOI wafers by bonding their bonding pads together, thereby producing a sandwiched wafer with first and second bottom or front-end-of-line (FEOL) surfaces facing outward and with first and second BEOL surfaces facing each other near the midline of the sandwiched wafer. The first SOI wafer then is prepared for packaging by first removing the silicon substrate from the first FEOL surface to reveal a buried oxide (BOX) layer, then fabricating interconnects atop the BOX layer and forming input output pads atop the interconnects.

The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

A process includes forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer including a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. A resultant article of manufacture is also disclosed.

A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200&#xb0; C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225&#xb0; C. The invention includes production of a product by this process and an article of manufacture embodying these features.

Enhanced via fill material and processing for dual damscene integration

Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Three-dimensional integrated circuit device fabrication including wafer scale membrane

A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

Capping coating for 3D integration applications

An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

Process for enhanced 3D integration and structures generated using the same

Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.

Corrugated interfaces for multilayered interconnects

A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

Lock and key through-via method for wafer level 3D integration and structures produced thereby

A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.

Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier

A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion.

Three-dimensional integrated circuit device using a wafer scale membrane

Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded only at the metal from the first substrate and the metal from the second substrate.

Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed

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Yorktown Heights, NY, United States of America

Sampath Purushothaman