Altera Corporation

Vlsi Technology, Inc.

Philips Electronics North America Corporation

Koninklijke Philips Corporation N.v.

Philips Semiconductors Inc.

Philips Semiconductor, Inc.

Samit S Sengupta

Subhas Bothra

Calvin T Gabriel

Cheng-Hsiung Huang

Hugh Sungki O

Tammy D Zheng

Kouros Ghandehari

Wei-Guang Wu

Dipankar Pramanik

Greg W Starr

Faran Nouri

Daniel C Baker

Edward K Yeh

Charles F Drill

Joseph Michael Ingino, Jr

In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.

Electrostatic discharge (ESD) protection device for use with multiple I/O standards

Techniques are provided for monitoring the performance of circuits and replacing low performing circuits with higher performing circuits. A frequency detector compares the frequency of a first periodic signal to the frequency of a second periodic signal. The difference in the frequency between the first periodic signal and the second periodic signal indirectly indicates how much the threshold voltages of the transistors have shifted. The difference in frequency between the two periodic signals can be monitored to determine the speed and performance of circuits on the chip. The output of the frequency detector can also indicate when to replace low performing circuits with higher performing circuits. When the frequency of the second periodic signal differs from the frequency of the first periodic signal by a predefined percentage, a low performing circuit is replaced with a higher performing replica circuit.

Techniques for monitoring and replacing circuits to maintain high performance

Integrated circuits are stabilized by monitoring changes that affect circuit operation and by compensating for those changes using power supply adjustments. Changes in operating temperature and threshold voltage changes may be measured. Differential measurements may be made in which threshold voltages measured in continuously-biased monitoring circuits are compared to threshold voltages measured in intermittently-biased monitoring circuits. Temperature changes may be monitored using a temperature monitoring circuit based on an adjustable current source and a diode. Monitoring and compensation circuitry on the integrated circuits may use analog-to-digital and digital-to-analog converters controlled by a control unit to make temperature and threshold voltage measurements and corresponding compensating changes in power supply voltages.

Integrated circuits with temperature-change and threshold-voltage drift compensation

A semiconductor device includes a substrate and a plurality of interconnect metallization lines defined over the substrate, each interconnect metallization line being provided with an electromigration-impeding composition including a percentage by weight of aluminum, a percentage by weight of copper, and a percentage by weight of zinc. The percentage by weight of zinc may be less than about 4 in solid solution in Al at 100 degrees C, which is a substantial increase in the Zn content over the about 0.5 weight percent of the Cu content in previously-used Al&mdash;Cu alloys. The percentage by weight of Zn may preferably range between about 1 and 2. The electromigration-impeding composition of the lines may include a structure of a solid solution of Al and Zn in the form of grains. The grains are bounded by grain boundaries. The structure further includes a precipitate of Al and Cu defined in the grain boundaries. Electromigration of the Al from the grain boundaries occurs and tends to cause the Al to electromigrate from the grains. The percentage by weight of Zn is selected to both define the solid solution with Al and to impede the electromigration of the Al from the grains. A method of making an interconnect metallization layer on a substrate includes depositing a metallization composition on the substrate, wherein the composition is the above-described composition.

Compositions for improving interconnect metallization performance in integrated circuits

A semiconductor device includes a semiconductor substrate, e.g., a part of a silicon wafer having an oxide layer disposed thereon. A metal stack is disposed over the semiconductor substrate and a dielectric layer is disposed over the metal stack. The dielectric layer has a via hole formed therein that is misaligned with the metal stack such that a portion of the via hole extends beyond the top of the metal stack and exposes at least a portion of one of the sidewalls of the metal stack. A sidewall cap layer is formed on the exposed portion of the sidewall of the metal stack. The sidewall cap layer is configured to resist substantial penetration of WF during chemical vapor deposition of tungsten. The sidewall cap layer may be a nitrided layer or a layer of a dielectric material. A conductive material comprised of tungsten is disposed in and substantially fills the via hole. Methods for making a conductive via in a semiconductor device are also described.

Semiconductor device with misaligned via hole

An apparatus for chemical-mechanical planarization (CMP) of semiconductor wafers that allows independent micro-control of each spindle for tailored CMP performance. The present invention provides, in one embodiment, a CMP tool that includes a stationary bridge that houses a rack and pinion assembly. The rack and pinion assembly is coupled to a plurality of motor assemblies each of which is coupled to rotate a spindle. Significantly, movements of the spindles across are individually and independently controlled by the rack and pinion assembly. An advantage of the present independent spindle motion design allows optimization of the CMP process for each spindle and enables more accurate prediction of the effect of translation on CMP performance. Independent rotation and downforce capability of the present invention provides additional flexibility in terms of tuning polish rates and uniformity. Another advantage of the present invention is that a more compact enclosure for wafer isolation can be achieved.

Apparatus for performing chemical-mechanical planarization with improved process window, process flexibility and cost

A semiconductor devices includes an anti-reflective structure for use in patterning metal layers in semiconductor devices. The anti-reflective structure is made, at least in part, using indium tin oxide. The anti-reflective structure is especially useful for patterning the metal layers with light having a wavelength of 190-300 nm. The anti-reflective structure may be a single indium tin oxide layer or may include a titanium nitride layer formed over the metal layer and an indium tin oxide layer formed over the titanium nitride layer. For many applications, the anti-reflective structure, in the presence of a photoresist layer, has a reflectivity of about 3% or less for light having a wavelength of 190-300 nm.

Semiconductor device with anti-reflective structure and methods of manufacture

In modern sub-micron technologies with aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized, and electrical connections are less susceptible to electromigration. Consequently, device yield and reliability are increased.

Optimized metal etch process to enable the use of aluminum plugs

For use with a sub-micron semiconductor process, a trench isolation process enables the formation of a wider isolation oxide around the shallow trench isolation (STI) opening. The wider oxide width minimizes the recessing of oxide along the trench sidewalls during subsequent cleaning and etching steps. In a method for forming STI regions on a silicon substrate having a buffer oxide thereon and a nitride layer on top of the buffer oxide, a mask layer is defined on the nitride layer patterning isolation regions in unmasked areas of the nitride layer. Isolation regions of sufficient depth are etched through in unmasked areas of the nitride layer, the buffer oxide and into the silicon substrate. Performing a lateral etch (a nitride shaving) of the nitride layer under the mask layer undercuts a portion of the nitride layer under the mask layer. After the lateral etch, the mask layer is removed. The STI region is filled with an oxide layer and is planarized until the oxide layer is substantially flush with the nitride layer. The resulting oxide layer is wider and protects the STI region from subsequent processing.

Method for forming isolation areas with improved isolation oxide

A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. The process includes forming a via in a device layer of the semiconductor device. A barrier layer is formed over the device layer and a metal layer is formed over the barrier layer. The metal layer also fills the via to form a via structure. A portion of the metal layer is then removed and a remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. A spacer is formed along the sidewall of the conductive structure and a portion of the barrier layer is removed using the spacer to protect the via structure adjacent the surface of the device layer. In particular, the spacer protects a portion of the via structure that does not overlap with the conductive structure.

Process for forming metal interconnects with reduced or eliminated metal recess in vias

A method for preparing a semiconductor substrate for subsequent silicide formation. In one embodiment, the present invention subjects the semiconductor substrate to an ashing environment. In the present embodiment, the ashing environment is comprised of H,O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants on the semiconductor substrate are removed. Next, the present invention subjects a mask covering a polysilicon stack to a mask-removal ashing environment. In the present embodiment, the mask-removal ashing environment is comprised of an O,plasma. In so doing, the mask covering the polysilicon stack is removed. As a result, the semiconductor substrate and the top surface of the polysilicon stack are prepared for subsequent silicide formation thereon.

Integrated process for ashing resist and treating silicon after masked spacer etch

The present invention provides methods of forming a semiconductor workpiece. One method of forming a semiconductor device in accordance with the present invention includes: providing a semiconductor workpiece; forming a via within the semiconductor workpiece, the via including plural sidewalls joining a bottom surface at respective plural corners; first sputtering a process layer upon at least a portion of the bottom surface using ionized metal plasma physical vapor deposition; and following the sputtering of the process layer, second sputtering at least some of the process layer towards the corners within the via.

Methods of forming a semiconductor device

Disclosed is a method for making a metallization layered stack over an oxide layer of a semiconductor substrate, and a metallization layered stack that assists in providing superior deep UV photolithography resolution. The method includes forming a bottom titanium nitride layer over the oxide layer, and forming an aluminum metallization layer over the bottom titanium nitride layer. The method further includes forming a top titanium nitride layer over the aluminum metallization layer, such that the forming of the top titanium nitride layer includes: (a) placing the semiconductor substrate in an ionized metal plasma chamber having an RF powered coil and a titanium target; (b) introducing an argon gas and a nitrogen gas into the ionized metal plasma chamber; (c) pressuring up the ionized metal plasma chamber to a pressure of between about 10 mTorr and about 50 mTorr, whereby the top titanium nitride layer is formed as a dense titanium nitride film.

Method for substantially preventing footings in chemically amplified

A semiconductor device includes a semiconductor substrate, e.g., a part of a silicon wafer having an oxide layer disposed thereon. A metal stack is disposed over the semiconductor substrate and a dielectric layer is disposed over the metal stack. The dielectric layer has a via hole formed therein that is misaligned with the metal stack such that a portion of the via hole extends beyond the top of the metal stack and exposes at least a portion of one of the sidewalls of the metal stack. A sidewall cap layer is formed on the exposed portion of the sidewall of the metal stack. The sidewall cap layer is configured to resist substantial penetration of WF.sub.6 during chemical vapor deposition of tungsten. The sidewall cap layer may be a nitrided layer or a layer of a dielectric material. A conductive material comprised of tungsten is disposed in and substantially fills the via hole. Methods for making a conductive via in a semiconductor device are also described.

Growing community of inventors

San Jose, CA, United States of America

Samit S Sengupta