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Fairchild Semiconductor Corporation

Samir M Laymoun

Roger V Rufford

Two pairs of bit lines are associated with each column of memory cells in a static random access memory (RAM) to provide separate paths for reading and writing operations or to provide a RAM having dual read ports. One pair of bit lines is connected to the emitters of the cross-coupled transistors in each cell to permit write operations to be carried out. The second pair of bit lines is connected to the collectors of clamping transistors which limit the collector voltage of the cell transistors, to permit data to be read.

Memory cell with separate read and write paths and clamping transistors

An improved memory cell circuit in which the collector of the 'ON' transistor is clamped to a variable voltage level to prevent saturation. Saturation is prevented by providing a mechanism for limiting the voltage between a first node in the word line circuit and the collector of the conducting transistor to a first level, while limiting the voltage between the first node and the collector of the nonconducting transistor to a second, lower level. In one embodiment, clamping transistors have their emitters coupled to the collectors of the memory cell transistors and their bases coupled to the word line. A common resistor couples the load resistors of a plurality of memory cells to the word line. In a second embodiment, the common resistor couples the bases of the clamping transistors to an intermediate node in a Darlington driver for the word line.

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Sunnyvale, CA, United States of America

Samir M Laymoun