Advanced Micro Devices Corporation

Spansion Llc.

Cypress Semiconductor Corporation

Other

Fujitsu Corporation

Semiconductor Components Industries, LLC

Advance Micro Devices, Inc.

Sameer S Haddad

Mark T Ramsbey

Chi K Chang

Richard M Fastow

Yu Nan Sun

Mark W Randolph

Steven C Avanzino

Vei-Han Chan

Shenqing Fang

Timothy J Thurgate

Unsoon Kim

Chun Chen

Kuo Tung Chang

Tuan Duc Pham

Colin Stewart Bill

Swaroop Kaza

Angela Tai Hui

Daniel Sobek

Christie Marrian

An Chen

Tzu-Ning Fang

Suzette Keefe Pangrle

Ravi S Sunkavalli

Ravi Prakash Gutala

James Minsu Pak

Lee Edward Cleveland

Hao Fang

Yue-Song He

Ashot Melik-Martirosian

Manuj Rathor

Zhigang Wang

Nicholas H Tripsas

Yi He

Chung-You Hu

Wai Lo

Wing Han Leung

John Chen

Fei Wang

Jeffrey Allan Shields

Pau-Ling Chen

Binh Quang Le

Shane Charles Hollmer

Zhizheng Liu

Bryan K Choo

Dongxiang Liao

Carl Robert Huster

James J Xie

Michael Vanbuskirk

Jonathan S Su

Janet S Wang

Nga-Ching Wong

Yi-Ching Jean Wu

Shoichi Kawamura

Seungmoo Choi

Kevin Song

Mike Van Buskirk

Matthew S Buynoski

Yowjuang William Liu

Scott D Luning

Michael Allen Van Buskirk

David K Liu

Ming Sang Kwan

Zhida Lan

Weidong Qian

Edward Franklin Runnion

Sheung-Hee Park

Janet S Y Wang

Sheunghee Park

Zhi-Gang Wang

Vei-Han Chen

Calvin T Gabriel

Hiroyuki Kinoshita

Darlene G Hamilton

Narbeh Derhacobian

Weize Chen

Tazrien Kamal

Yuan Tang

Ming-Huei Shieh

Xin Sheng Guo

Youseok Suh

Jean Yee-Mei Yang

Inkuk Kang

Mark Griswold

Scott Luning

Di Li

Emmanuil Lingunis

Cinti Xiaohua Chen

Nader A Radjy

Michael Van Buskirk

Tim Thurgate

Joseph G Pawletko

Bruce Greenwood

Kelwin Ko

Zengtao Liu

Boon-Yong Ang

Kenneth Andrew Bates

Hajime Wada

Eric M Ajimine

Jonathan Shi-Chang Su

Mong-Song Liang

An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

Process of forming an electronic device including a non-volatile memory cell

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

Memory first process flow and device

A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.

Charge trapping split gate device and method of fabricating same

Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.

Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.

Charge trapping split gate embedded flash memory and associated methods

A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.

An example system includes a processing circuit coupled to a memory system and an interface coupled between the processing circuit and a device. The memory system includes a resistive memory array comprising multiple memory structures. Each memory structure comprises a resistive memory cell and is associated with a P-I-N diode. The processing circuit is to access the resistive memory array responsive to a signal received from the device via the interface.

Resistive memory array using P-I-N diode select device and methods of fabrication thereof

An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device&#x2014;P-I-N diode structures.

A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level.

Modified local segmented self-boosting of memory cell channels

Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.

A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Damascene metal-insulator-metal (MIM) device with improved scaleability

In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.

Metal-insualtor-metal (MIM) device and method of formation thereof

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San Jose, CA, United States of America

Sameer S Haddad