Elantec Semiconductor, Inc.

Sameer Parab

Mark A Salsbery

A silicon on insulator substrate is provided to include the following: a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from the layer of bonding material upward into the device wafer; and an epitaxial silicon layer provided on a second surface of the device wafer. The silicon on insulator substrate with this configuration can be made with a minimal possible thickness.

Reduced substrate capacitance high performance SOI process

A method for forming a semiconductor substrate is provided including the general sequential steps of: providing a handle wafer and a device wafer; implanting at least a first impurity region in a first surface of the device wafer; bonding the first surface of the device wafer to a first surface of the handle wafer having a silicon dioxide layer; removing a portion of the device wafer at a second surface; and forming an epitaxial silicon layer on the second surface of the device wafer. The process enables the thickness of the device wafer to be minimal.

A liquid etch apparatus including an outer tank for holding a liquid etch solution, which has included therein an inner cylindrical member positioned in the outer tank. At one end of the inner cylindrical member, a sparger or other gas supply means may be provided. Filters are provided between the inner cylindrical member and the outer tank. Substrates are secured in the inner tank and a propeller is provided below the substrates. Gas is introduced into the inner cylindrical member during the etch process which creates a pressure gradient between the inner tank and the outer tank, forcing particulate matter carried by the gaseous particles to circulate around to the filters.

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Milpitas, CA, United States of America

Sameer Parab