Cadence Design Systems, Inc.

Sameer Chakravarthy Chillarige

Anil Malik

Joseph Michael Swenton

Sharjinder Singh

Krishna Chakravadhanula

Sonam Kathpalia

Bharath Nandakumar

Mehakpreet Kaur

Vivek Chickermane

Brian Edward Foutz

Brion L Keller

Patrick Gallagher

Shaleen Bhabu

Gilbert C Vandling

Sarthak Singhal

Prateek Kumar Rai

James S Allen

Joe Swenton

Robert Jordan Asher

Nilabha Dev

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group. The test-point flop allocation module can further allocate one of the test-point flops to each of the test-point sharing groups. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist. The circuit layout is employable to fabricate an IC chip.

Clock-based test-point flop sharing in a circuit design

Scan channel slicing methods and systems for testing of scan chains in an integrated circuit (IC) reduce the number of test cycles needed to effectively test all the scan chains in the IC, reducing the time and cost of testing. In scan channel slicing, rather than loading and unloading into scan chains high-power patterns having numerous switching transitions over the length of each scan chain, loading and unloading the entirety of the scan chain scan while observing it, chain load data is sliced, apportioning between the different scan chains independently observable sections (slices) of transition data in which all four bit-to-bit transitions ('0' to '0', &#x201c;0&#x201d; to &#x201c;1&#x201d;, &#x201c;1&#x201d; to 0&#x201d;, &#x201c;1&#x201d; to &#x201c;1&#x201d;) are ensured to exist. The remainder of the scan chain load data, which is not observed in the test procedure, can be low-transition data that consumes low dynamic power, such as mostly zeroes or mostly ones.

Scan channel slicing for compression-mode testing of scan chains

Systems and methods for multiple device diagnostics are disclosed herein. Exemplary embodiments provide for a multiple device diagnostic system having a plurality of electronic devices selected for diagnosis based on at least one selection criterion, a diagnosis engine in data communication with a failure database, and a diagnosis results database in data communication with the diagnosis engine. Embodiments further provide that the failure database contains grouped failure data from at least one previously diagnosed electronic device, that the wherein the processor diagnoses defects in one or more of the plurality of electronic devices using the grouped failure data, and that the processor outputs the diagnosis results to the diagnosis results database.

System and method for multiple device diagnostics and failure grouping

Systems and methods for creating learning-based personalized user interfaces for software applications are described. Exemplary embodiments provide for collecting usage data and applying machine learning techniques to identify and prioritize certain commands and options in the personalized user interface. The usage data can include Usage patterns, usage sequences, and the usage of certain commands and options in connection with, or following, certain other commands and options may also be identified, and the personalization-based prioritization can include, for example, the contents, position, and quantities of the commands and options within the interface.

Systems and methods for creating learning-based personalized user interfaces

A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.

Highly accurate defect identification and prioritization of fault locations

An integrated circuit test method provides an interactive shell environment having analysis modules organized as a directory such that for a given session a user can access any of the analysis modules. This invention describes a virtual directory structure for navigating through the entire test data starting from design, test configuration, ATPG patterns, failure information and callout information. This structure also allows the creation of a scripting environment for the user to select a specific configuration and process the information. User can achieve all of this in a single session as opposed to working on every test configuration in an independent session.

Virtual directory navigation and debugging across multiple test configurations in the same session

The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to process. The method may further include selecting a sliced failing pattern set and generating a plurality of copies of a pattern associated with the sliced failing pattern set, wherein each of the plurality of copies corresponds to one of the plurality of defect locations. The method may also include simulating the plurality of copies of the pattern in parallel.

System and method performing scan chain diagnosis of an electronic design

Systems and methods disclosed herein provide for automatically diagnosing mis-compares detected during simulation of Automatic Test Pattern Generation ('ATPG') generated test patterns. Embodiments of the systems and methods provide for determining the origin of a mis-compare based on an analysis of the generated test patterns with a structural simulator and a behavioral simulator.

Method and apparatus for automatic diagnosis of mis-compares

Embodiments for diagnosing failure locations in one or more electronic circuits. Embodiments may include generating a plurality of core instances of at least one core, for each electronic circuit, with one or more outputs and compressing the outputs of each instance into primary output pins based upon compression equations. Embodiments may include applying test patterns to the plurality of core instances and identifying failures based upon compressed test patterns received at the primary output pins. Embodiments may include performing fault selection on a single core instance for each failure associated with the plurality of core instances and performing fault simulations on the single core instance for each candidate faults associated with the plurality of core instances. Embodiments may include generating fault signatures for each detected fault based upon the instances associated with each detected fault and analyzing each fault signature to determine failure locations.

System and method for diagnosing failure locations in electronic circuits

In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the individual chips, to determine if a fault candidate generates all failures for a chip and no others. The test inputs and expected outputs may be predetermined through Automatic Test Pattern Generation. The fault candidates may be determined by use of a backtrace process such as back cone tracing. The failures may be recorded in association with a measure point, the input pattern that resulted in the failure, and the failure value.

Method and system of collective failure diagnosis for multiple electronic circuits

An apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan chain is generated from at least a portion of the flip flops in the first group. At least one scan chain is generated from at least a portion of the flip flops in the second group.

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Uttar Pradesh, India

Sameer Chakravarthy Chillarige