Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Braodcom Corporation

Avago Technologies General IP Pte, Ltd.

Sam Ziqun Zhao

Rezaur Rahman Khan

Reza-ur Rahman Khan

Ahmadreza Rofougaran

Arya Behzad

Michael Boers

Jesus Alfonso Castaneda

Pieter Vorenkamp

Xiangdong Chen

Kevin Kunzhong Hu

Edward Law

Sampath K V Karikalan

Liming Tsau

Sam Komarapalayam Karikalan

Marc Papageorge

Arun Ramakrishnan

Reza Sharifi

Mayank Mayukh

Dharmendra Saraswat

Brent Bacher

Frank Hui

Andy Brotman

Imtiaz Chaudhry

Sampath Komarapalayam Karikalan

Milind S Bhagavat

Chonghua Zhong

Victor Fong

Neal Andrew Kistler

Nir Matalon

Fan Yeung

Ming Wang Sze

Galen Kirkpatrick

Reza Khan

Seyed Mahdi Saeidi

Calvin Wong

Reaz-ur Rahman Khan

Mehdi Saeidi

Arpit Mittal

Kunzhong Hu

Arya Reza Behzad

Kevin Hu

Sampath Karikalan

A semiconductor package with integrated side wall antennas is provided. An apparatus includes two or more die layers that are bonded together, each of the two or more die layers comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes a first antenna array, the first antenna array comprising a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements is at least partially exposed at the first side wall.

Integrated antennas on side wall of 3D stacked die

It is described a interconnect array device (e.g., Ball Grid Array (BGA) device) comprising (a) a substrate having a substrate body and a main surface; (b) an array of solder connection elements formed at the main surface; and (c) a support structure formed at the main surface. The support structure is configured for maintaining, during a soldering process, a predefined spacing between the main surface of the substrate and a further main surface of a component carrier onto which the Ball Grid Array is mounted. The support structure comprises at least one support element. Further described is an electronic package with such a Ball Grid Array device and a method for manufacturing an electronic assembly comprising such an electronic package mounted on a component carrier.

Interconnection array device with support

A package, and method for building the package is disclosed. The package includes a substrate having a first surface. The package further includes a die having opposing first and second surfaces, and a lateral surface, with the second surface of the die coupled to the first surface of the substrate. The package further includes a stiffener element having a first surface and a lateral surface, with the first surface of the stiffener element coupled to the first surface of the substrate. The package further includes molding material disposed on the first surface of the substrate and the lateral surface of the die. The coefficient of thermal expansion (CTE) value of the molding material is greater than a CTE value of the die. The first molding surface of the molding material is coplanar with the first surface of the die.

Stress and warpage improvements for stiffener ring package with exposed die(s)

Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.

Cantilevered power planes to provide a return current path for high-speed signals

An apparatus includes a substrate that includes one or more routing layers, and an optical module coupled to the substrate. The optical module includes a photonic integrated circuit (PIC) and electronic integrated circuit (EIC), wherein the photonic integrated circuit is at least partially embedded within the substrate. The apparatus further includes a fiber optic coupler coupled to at least one of the substrate or PIC, wherein the PIC is configured to transmit or receive an optical signal via the fiber optic coupler.

Photonics integration in semiconductor packages

An integrated circuit die includes a metal layer, a first passivation layer disposed above the metal layer, an aluminum containing redistribution layer disposed above the first passivation layer, an under bump metallization layer, and a redistribution layer plug. The redistribution layer plug is coupled to the metal layer and disposed in a via in the first passivation layer. The under bump metallization layer is coupled to the aluminum containing redistribution layer above the first passivation layer at a distance from the redistribution layer plug.

Redistribution metal and under bump metal interconnect structures and method

Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer. The circuit assembly further includes an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps and an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.

Thin recon interposer package without TSV for fine input/output pitch fan-out

An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/output pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package. Embodiments of the present disclosure further enable lower manufacturing costs because of the use of mature reconstituted dies and redistribution layer technologies and the lack of a need for an interposer to connect multiple dies.

High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer

In embodiments described herein, an integrated circuit (IC) package is provided. The IC package may include a substrate, an IC die, and a heat spreader. The IC die may have opposing first and second surfaces, where the first surface of the IC die is coupled to a surface of the substrate. The heat spreader may have a surface coupled to the second surface of the IC die by a thermal interface (TI) material. The surface of the heat spreader may have a micro-recess which may include a micro-channel or a micro-dent to direct a flow of TI material towards or away from a predetermined area of the second surface of the IC die based on temperatures of the substrate, the IC die, and/or the heat spreader.

Heat spreader having thermal interface material retainment

Disclosed herein are systems, apparatuses, and methods for locating wireless-enabled components, and applications thereof. Such an apparatus includes a wireless-enabled component (WEC), which may be a functional block of an integrated circuit (IC), an IC, or a device that includes an IC. The WEC includes a functional module (e.g., a processing resource or a memory resource) and an antenna element coupled to the functional module. The antenna element is configured to (i) transmit a search signal to locate a proximally situated WEC and (ii) transmit a communication signal to communicate with the proximally situated WEC. The antenna element may be a phased array, an electrically steered phased array, a mechanically steered phased array, a directional antenna, a mechanically steered directional antenna, an RF antenna, an optical antenna, and/or any combination thereof.

Locating wireless-enabled components and applications thereof

Embodiments of the present invention are directed to a wireless-enabled component (WEC) for enabling a wireless bus for intra-chip and inter-chip communication. A WEC encompasses a functional block of an IC (such as, for example, a processing core of a processing unit), an entire IC (such as, for example, a processing unit), or a device that includes a plurality of ICs (such as, for example, a handheld device). According to embodiments, a WEC may be associated with one or more sub-blocks of an IC, a single IC, or a plurality of ICs.

Wireless bus for intra-chip and inter-chip communication, including wireless-enabled component (WEC) embodiments

A package such as a system in package (SiP) includes a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first mold and a second die disposed in a second mold layer and coupled to a second dielectric layer disposed above the second die. A pillar is disposed through the second mold layer and is coupled to a first metal layer disposed above the first dielectric layer. The first metal layer is coupled to the first die, and the pillar is coupled to a second metal layer disposed above the second dielectric layer.

Wafer level system in package (SiP) using a reconstituted wafer and method of making

A three-dimensional (3D) integrated circuit (IC) package is disclosed that contains a plurality of encapsulated layers stacked upon each other without the use of a substrate(s). Each of the encapsulated layers contains an encapsulating material, a die, an interconnecting interface, and vertical vias. The encapsulating material forms the surfaces of an encapsulated layer and encapsulates the die. The interconnecting interface provides an interface at a surface of the encapsulated layer for the die to electrically connect to other dies or external components. The vertical vias provide a conduction path between interconnecting interfaces of different encapsulated layers.

Fan-out 3D IC integration structure without substrate and method of making the same

Growing community of inventors

Irvine, CA, United States of America

Sam Ziqun Zhao