Catalyst Semiconductor, Inc.

Sam S Chu

Calvin V Ho

A structure and method are provided which reduce memory cell size by forming self-formed contacts and self-aligned source lines in the array. In one embodiment of the present invention, a plurality of self-aligned memory cells are formed in an array. Then, a first insulating layer is deposited on the array, and subsequently etched to form spacers on the sidewalls of each memory cell. Conductive plugs are then formed between adjacent spacers. Subsequently, a second insulating layer is deposited over the array. Finally, drain contacts are formed through the second insulating layer a first set of plugs. Other plugs form source lines for the array. Because the present invention provides a self-formed contact, only the second insulating layer is etched to establish contact between a metal bit line and an underlying diffused drain region. Thus, the present invention ensures appropriate isolation for each memory cell while reducing the area required for contact formation. In this manner, the self-formed contact allows for significant size reduction of the contact pitch. Moreover, using other plugs to form the self-aligned source lines of the array further reduces the size of the word line pitch, thereby dramatically reducing the associated cell size and allowing formation of ultra-high density memory arrays. Additionally, other metal self-aligned source significantly reduces source line resistance, thereby eliminating the need for frequent source line contacts, increasing cell efficiency and improving cell performance.

Structure and method for improved memory arrays and improved electrical

A structure and method are provided which reduce memory cell size by forming self-formed contacts and self-aligned source lines in the array. In one embodiment of the present invention, a plurality of memory cells are formed in an array. Then, a first insulating layer is deposited on the array, and subsequently etched to form spacers on the sidewalls of each memory cell. Conductive plugs are then formed between adjacent spacers. Subsequently, a second insulating layer is deposited over the array. Finally, drain contacts are formed through the second insulating layer to a first set of plugs. Other plugs form source lines for the array. Because the present invention provides a self-formed contact, only the second insulating layer is etched to establish contact between a metal bit line and an underlying diffused drain region. Thus, the present invention ensures appropriate isolation for each memory cell while reducing the area required for contact formation. In this manner, the self-formed contact allows for significant size reduction of the contact pitch. Moreover, using other plugs to form the self-aligned source lines of the array further reduces the size of the word line pitch, thereby dramatically reducing the associated cell size and allowing formation of ultra-high density memory arrays.

Word line stress is used to narrow the distribution of threshold voltages after an erase of an array of memory cells. One embodiment of the invention provides a method for erasing an array including a standard erase technique followed by extra erase pulses to create a margin between threshold voltages of the cells and the erase verify level, then applying word line stress to narrow the distribution of threshold voltages. Another embodiment in addition includes verifying that all of the memory cells are still erased after applying word line stress and if any of the memory cells were over-stressed and are not erased, repeating the method but using less word line stress. The erase methods according to embodiments of the present invention can be implemented by an external CPU which executes an erase program or by circuitry embedded in an EEPROM.

Growing community of inventors

San Jose, CA, United States of America

Sam S Chu