Spansion Llc.

Cypress Semiconductor Corporation

Advanced Micro Devices Corporation

Sally Foong

Lai Nguk Chin

Kevin Guan

Kwet Nam Wong

Wong Kwet Nam

Cheng Sim Kee

Nguk Chin Lai

Foong Yue Ho

Seshasayee Gaddamraja

Suthakavatin Aungkul

Teoh Lai Beng

Royce Yeoh Kao Tziat

Yue Ho Foong

Thor Lee Lee

L K Suresh

Paphat Phaoharuhan

Kanchit Suphanpeasat

Koo Eng Luon

Changhak Lee

Tan Kiah Ling

Kee Cheng Sim

According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame. An adhesive paste is then applied to attach the semiconductor die to the lead frame such that the adhesive paste fixes the die to a portion of the lead frame. The adhesive paste may be applied directly between die and the lead frame or may be applied in conjunction with a frame tape.

Tape chip on lead using paste die attach material

Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers.

Method of chip positioning for multi-chip packaging

Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.

Chip positioning in multi-chip package

A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.

Method and system for thin multi chip stack package with film on wire and copper wire

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Stitch bump stacking design for overall package size reduction for multiple stack

A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.

Reduction of package height in a stacked die configuration

Methods and systems of applying a plurality of pieces of die attach film to a plurality of singulated dice are provided. The method can involve making intervals between rows and columns of a plurality of pieces of die attach film. The interval can be made by expanding an underlaid expandable film on which the plurality of pieces of die attach film are placed or by removing portions of the die attach film between rows and columns of the plurality of pieces of die attach film. The method can further involve placing a plurality of singulated dice back side down on the plurality of pieces of die attach film.

Process applying die attach film to singulated die

A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate.

Die offset die to die bonding

Die offset die to bonding

Segmentation of a flexible, elongated, strip-shaped substrate having a plurality of encapsulated semiconductor devices mounted thereon, for device singulation, is facilitated by pre-cutting pairs of slots through the substrate at each device mounting area, which slots minimize the amount of substrate material required to be removed during device singulation. Disadvantageous penetration of the slots by liquid encapsulant material is substantially prevented, or at least minimized, by forming slots having burrs or flaps at the upper, mounting surface of the substrate which seal off, or substantially reduce the width of the slots.

Growing community of inventors

Milpitas, CA, United States of America

Sally Foong