Globalfoundries Inc.

Intermolecular, Inc.

Salil Mujumdar

Paul Raymond Besser

Hoon Sik Kim

Kisik Choi

Amol Ramesh Joshi

Jinping Liu

Olov B Karlsson

Ashish Bodke

Zhendong Hong

Usha Raghuram

Divya Pisharoty

Susie Tzeng

Chi-I Lang

Edward L Haywood

Albert Sanghyup Lee

Sandip Niyogi

ALD of HfAlCfilms using hafnium chloride (HfCl) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfClpulse time allows for control of the Al % incorporation in the HfAlCfilm in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfAlCwork function layer coupled with ALD deposited HfOhigh-k gate dielectric layers was quantified to be mid-gap at &#x2dc;4.6 eV. Thus, HfAlCis a promising metal gate work function material allowing for the tuning of device threshold voltages (V) for anticipated multi-Vintegrated circuit (IC) devices.

Atomic layer deposition of HfAlC as a metal gate workfunction material in MOS devices

An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Gate structures for transistor devices for CMOS applications and products

Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.

Method to control depth profiles of dopants using a remote plasma source

One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Methods of forming gate structures for transistor devices for CMOS applications

Growing community of inventors

San Jose, CA, United States of America

Salil Mujumdar