Intel Corporation

Other

The B. F. Goodrich Company

Promerus, Lcc

Sumitomo Bakelite Company Limited

International Business Machines Corporation

Ravikiran, Ramakrishna

Saikumar Jayaraman

Larry Funderburk Rhodes

Brian L Goodall

Robert A Shick

Ashay A Dani

Paul A Koning

Richard Vicari

Robert David Allen

Ratnam Sooriyakumaran

Rahul N Manepalli

Andrew Bell

Edmund Elce

Daewoong Suh

Richard Anthony DiPietro

Christopher L Rumer

Stephen Edward Lehman, Jr

James Chris Matayabas, Jr

Xiaoming Wu

Takashi Hirano

Sabina J Houle

Edward Rudolph Prack

Sriram Muthukumar

Dingying David Xu

George M Benedikt

Nisha Ananthakrishnan

Yiqun Bai

Anna M Prakash

Debendra Mallik

Gregory Martin Chrysler

Kemal Aygun

John Stephen Guzek

Pushkara Rao Varanasi

Zhiguo Qian

Shigeki Tomishima

Hiroshi Ito

Christine Nicole Elia

Andrew Paul Collins

Edvin Cetegen

Joe F Walczyk

Xavier Francois Brun

Makarem A Hussein

Jianyong Xie

Srikant Nekkanty

Hendra Ng

Wei Zhang

Ayusman Sen

Tian-An Chen

Brian F Knapp

Yidnekachew S Mekonnen

Gregorio R Murtagian

John-Henry Lipian

Thomas Ingolf Wallow

Ramakrishna Ravikiran

Vijay Wakharkar

Mitesh C Patel

Juliann Opitz

John C Fondran

Sheau Hooi Lim

Richard A Mimna

Yoong Tatt P Chin

Terry Lee Sterrett

Arjun Krishnan

Suriyakala Ramalingam

Shenliang Sun

Mihir A Oka

Lester H McIntosh, Iii

Yonghao Xiu

Hirotaka Nonaka

Robert John Duff

Edward L Martin

Sivakumar Nagarajan

Tiffany Byrne

Yuying Wei

Wei Keat Loh

Jeffrey C Krotine

Beverly J Canham

Stephen E Lehman

W Chris McDougall

Hiroko Nakano

Huabin Wang

Mohd Erwan B Basiron

Rubayat Mahmud

Aastha Uppal

George Vakanas

Etsu Takeuchi

Feroz Mohammad

Aaron McCann

Tannaz Harirchian

Rajesh Raja Puthenkovilakom

David Kehlet

Jennifer D Polley

Kabirkumar Mirpuri

April D Hennis

Prasad Ramanathan

William DiMenna

Tian An Chen

Ravi Ravikiran

Mohd Erwan P Bin Basiron

Yí Li

Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.

Micro socket electrical couplings for dies

A first semiconductor device includes a processor configured to generate a random number at initial test of a second semiconductor device after fabrication of the second semiconductor device in a supply chain related to the second semiconductor device, and send the generated random number to the second semiconductor device. The processor is further configured to receive a first signature that is signed over the sent random number by the second semiconductor device using a first private key that is stored in the second semiconductor device, among a first private and public key pair, and test the received first signature, using a first public key that is stored in the first semiconductor device, among the first private and public key pair, to determine whether the second semiconductor device is authenticated.

Systems and methods for device authentication in supply chain

Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

Thermally-optimized tunable stack in cavity package-on-package

Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

Architecture and processes to enable high capacity memory packages through memory die stacking

An electronic device may include a semiconductor package, that may include a package substrate. The package may include a semiconductor die. A plurality of package interconnects may include a first pillar extending from a surface of the package substrate. The electronic device may include a socket that may be configured to couple with the semiconductor package. The socket may include a plurality of socket interconnects configured to engage with the package interconnects. The plurality of socket interconnects may include a first contact, and the first contact may include an arm. The arm of the first contact may be configured to engage with the first pillar, and the arm may be configured to laterally displace when engaged with the first pillar. The engagement of the arm with the first pillar may establish an electrical communication pathway between the semiconductor package and the socket.

Pillar based socket

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.

Methods of promoting adhesion between underfill and conductive bumps and structures formed thereby

Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.

Forming a stress compensation layer and structures formed thereby

Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.

Integrated circuit package stack

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Integrated WLUF and SOD process

This disclosure relates generally to generating a solder-on-die using a water-soluble resist, system, and method. Heat may be applied to solder as applied to a hole formed in a water-soluble resist coating, the water-soluble resist coating being on a surface of an initial assembly. The initial assembly may include an electronic component. The surface may be formed, at least in part, by an electrical terminal of the electronic component, the hole being aligned, at least in part, with the electrical terminal. The solder may be reflowed, wherein the solder couples, at least in part, with the electrical terminal.

Solder-on-die using water-soluble resist system and method

Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications.

Thermoset polymides for microelectronic applications

Techniques are disclosed for protecting a surface using a dry-removable protective coating that does not require chemical solutions to be removed. In an embodiment, a protective layer is disposed on a surface. The protective layer is composed of one layer that adheres to the surface. The surface is then processed while the protective coating is on the surface. Thereafter, the protective layer is removed from the surface by separating the protective layer away from the surface without the use of chemical solutions.

Dry-removable protective coatings

Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.

Polymer matrices for polymer solder hybrid materials

Growing community of inventors

Chandler, AZ, United States of America

Saikumar Jayaraman