Motorola Corporation

Freescale Semiconductor,inc.

Other

Everspin Technologies, Inc.

Saied N Tehrani

Herbert Goronkin

Eugene Youjun Chen

Mark A Durlam

Jun Shen

Xiaodong T Zhu

Jon Michael Slaughter

X Theodore Zhu

Kelly Wayne Kyler

Theodore Zhu

Gloria J Kerszykowski

Mark DeHerrera

Jenn-Hwa Huang

Majid M Hashemi

Nicholas David Rizzo

Jing Shi

Thomas Andre

Vijay K Nair

Bradley Neal Engel

Peter K Naji

Raymond K Tsui

Marino J Martinez

Michael S Lebby

Joseph J Nahas

Gregory W Grynkewich

Brian R Butcher

Ronald N Legge

Clarence J Tracy

Kumar Shiralagi

Bradley J Garni

Rimantas L Vaitkus

Ernie Schirmann

Jason A Janesky

William J Ooms

Jonathan K Abrokwah

Robert T Smith

Ernest Schirmann

Renu Whig Dave

Mark F Deherrera

Sung P Pack

Steven A Voight

John J D'Urso

Patricia A Norton

Herb Goronkin

Martin Walther

David W Cronk

Vernon Patrick O'Neil, Ii

Clarance J Tracy

Farideh Nikpourian

An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied.

Structures and methods for a field-reset spin-torque MRAM

An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element () including a first electrode (), a second electrode () and a spacer layer (). The first electrode () and the second electrode () include ferromagnetic layers (&). A spacer layer () is located between the ferromagnetic layer () of the first electrode () and the ferromagnetic layer () of the second electrode () for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (&). The device includes insulative veils () characterized as electrically isolating the first electrode () and the second electrode (), the insulative veils () including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element () with insulative veils () that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.

Magnetic element with insulating veils and fabricating method thereof

An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

MRAM and methods for reading the MRAM

An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

MRAM architecture

An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element ( ) including a first electrode ( ), a second electrode ( ) and a spacer layer ( ). The first electrode ( ) and the second electrode ( ) include ferromagnetic layers ( & ). A spacer layer ( ) is located between the ferromagnetic layer ( ) of the first electrode ( ) and the ferromagnetic layer ( ) of the second electrode ( ) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers ( & ). The device includes insulative veils ( ) characterized as electrically isolating the first electrode ( ) and the second electrode ( ), the insulative veils ( ) including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element ( ) with insulative veils ( ) that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.

Method of fabricating a magnetic element with insulating veils

A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.

Method of fabricating a self-aligned via contact for a magnetic memory element

A magnetic layer ( ) of a magnetoelectronics element ( ) is provided that has a first sub-element layer ( ) and a second sub-element layer ( ). The first sub-element layer ( ) is configured to have a first area and the second sub-element layer ( ) is configured to have a second area that is less than the first area.

Magnetoelectronics element having a magnetic layer formed of multiple sub-element layers

An MTJ cell including an insulator layer of material between magnetic material layers with the insulator layer of material having a greater attraction for a third material than the magnetic material layers. The third material is introduced to one or both so that when the cell is heated the third material is redistributed from the magnetic material layer to the insulator layer. Upon redistribution the insulator layer becomes an insulator layer material. Also, a first diffusion barrier layer is positioned between a first metal electrode and one of the magnetic material layers and/or a second diffusion barrier layer is positioned between a second metal electrode and the other magnetic material layer to prevent diffusion of the metal in the electrodes into the magnetic material layers.

Method of fabricating thermally stable MTJ cell and apparatus

A magnetoresistive random access memory architecture free of isolation devices includes a plurality of data columns of non-volatile magnetoresistive elements. A reference column includes non-volatile magnetoresistive elements positioned adjacent to the data column. Each column is connected to a current conveyor. A selected data current conveyor and the reference current conveyor are connected to inputs of a differential amplifier for differentially comparing a data voltage to a reference voltage. The current conveyors are connected directly to the ends of the data and reference bitlines. This specific arrangement allows the current conveyors to be clamped to the same voltage which reduces or removes sneak circuits to substantially reduce leakage currents.

MRAM without isolation devices

A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.

High density MRAM cell array

A magnetic memory cell (,) has a semiconductor layer (,) positioned between first (,) and second (,) ferromagnetic layers forming either a p-n or Schottky junction. A magnetic layer (,) is positioned between the first ferromagnetic layer and a digit line (first) for pinning a magnetic vector within the second ferromagnetic layer. In a,embodiment, a gate contact (,) is spaced apart from the layer of semiconductor material for controlling the electron flow through the semiconductor layer.

MRAM having semiconductor device integrated therein

An improved and novel magnetic element (,) including a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field. Additionally disclosed is a method of fabricating a magnetic element (,) by providing a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields of the thin film layers cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field.

Magnetic element with dual magnetic states and fabrication method thereof

A method of fabricating a flux concentrator for use in magnetic memory devices including the steps of providing at least one magnetic memory bit (,) and forming proximate thereto a material stack defining a copper (Cu) damascene bit line (,) including a flux concentrating layer (,). The method includes the steps of depositing a bottom dielectric layer (,), an optional etch stop (,) layer, and a top dielectric layer (,) proximate the magnetic memory bit (,). A trench (,) is etched in the top dielectric layer (,) and the bottom dielectric layer (,). A first barrier layer (,) is deposited in the trench (,). Next, a metal system (,) is deposited on a surface of the first barrier layer (,). The metal system (,) includes a copper (Cu) seed material (,), and a plated copper (Cu) material (,), a first outside barrier layer (,), a flux concentrating layer (,), and a second outside barrier layer (,). The metal system (,) is patterned and etched to define a copper (Cu) damascene bit line (,).

Method of fabricating flux concentrating layer for use with magnetoresistive random access memories

An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (,) including a first electrode (,), a second electrode (,) and a spacer layer (,). The first electrode (,) includes a fixed ferromagnetic layer (,). A second electrode (,) is included and comprises a free ferromagnetic layer (,). A spacer layer (,) is located between the fixed ferromagnetic layer (,) and the free ferromagnetic (,) layer, the spacer layer (,). At least one additional layer (,&,) is provided between the base metal layer (,) and the spacer layer (,). The base metal layer (,) or at least one of the layers positioned between the base metal layer (,) and the spacer layer (,) having an x-ray amorphous structure such that a reduced topological coupling strength between the free ferromagnetic layer (,) and the fixed ferromagnetic layer (,) is achieved.

Magnetic element with improved field response and fabricating method thereof

A multi-layer magnetic material (,) has magnetic vectors (,) that point along a length (,) of the material (,). Opposing magnetic fields cause the vectors to snap past the perpendicular position with a rapid change in the resistance of the material. The material is used as a memory cell (,) of a memory (,).

Ferromagnetic GMR material and method of forming and using

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Tempe, AZ, United States of America

Saied N Tehrani