Sanyo Electric Co., Ltd.

Sanyo Semiconductor Co., Ltd.

Semiconductor Components Industries, LLC

On Semiconductor Trading, Ltd.

Sadao Yoshikawa

Toshiki Rai

Tomofumi Watanabe

Yoh Takano

Takayuki Suzuki

Noriaki Kojima

Masanori Kajitani

Yasuhiro Kobayashi

Kenya Uesugi

Norihiko Kubota

Jumpei Maruyama

Toshihiro Itagaki

Sigenori Shibata

Shigenori Shibata

With a serial interface memory device of this invention, a read-out rate of data is increased, while an increase in a size of a circuit is suppressed. An EEPROM is provided with a memory cell array storing data, a row address decoder and a column address decoder that select an address of the memory cell array in accordance with an address signal serially inputted in synchronization with a clock, sense amplifiers SA-SA, SA_Mand SA_Meach provided corresponding to each bit of the data, and a shift register that outputs the data read out from the sense amplifiers serially from a first bit. The column address decoder commences reading out two candidate data for the first bit by inputting each of the two candidate data to each of the two sense amplifiers SA_Mand SA_M, respectively, before all bits of the column address signal are established.

Memory device

A reset transistor is prevented from being deteriorated when power-down occurs during a programming operation or an erasing operation. It is made possible to protect the reset transistor as well as other transistors in a circuit to which a high voltage is applied when the power-down occurs during the erasing operation on an EEPROM, because the system is not reset all at once based only on a first reset signal POR of a power-on reset circuit, but is reset based on the first reset signal POR and a low voltage detection signal LD from a low voltage detection circuit so that the reset transistor is not turned on while the high voltage is applied to it.

Reset circuit of high voltage circuit

This invention offers a semiconductor memory device, with which a resolution to read-out data is not reduced even at the time of verify and a stable read-out operation is possible even when a power supply voltage is reduced. A read-out circuit is provided with a current-voltage conversion circuit, that converts a cell current into a data voltage, and a sense amplifier that compares the data voltage with a reference voltage. The current-voltage conversion circuit is formed to include a variable load resistor that is connected to the memory cell through a bit line. The variable load resistor is formed to include P channel type MOS transistors that make load resistors and P channel type MOS transistors that constitute a switching circuit.

Semiconductor memory device

A memory device including a serial-parallel conversion section that converts serial data into parallel data, a parallel-serial conversion section that converts parallel data into serial data, and a parallel-parallel conversion section that changes a bit width of the parallel data. This memory device connects one external terminal to the serial-parallel conversion section and another external terminal to the parallel-serial conversion section when access using a serial interface is performed. On the other hand, the memory device connects a plurality of external terminals to the parallel-parallel conversion section when access using a parallel interface is performed, thereby enabling the memory device to occasionally realize parallel transfer of data while using a conventional package.

Memory device with parallel interface

There is offered a semiconductor memory device that has reduced number of high withstand voltage transistors so as to suppress an increase in a die size. A second transistor of N channel type is connected between a word line and a decoder circuit. A control signal from a control circuit is applied to a gate of the second transistor. When an output of the decoder circuit is at a low level, the word line is in a non-selected state, and a high voltage from a switching circuit is not outputted to the word line. Instead, the word line is provided with the ground voltage (=non-erasing voltage) from the decoder circuit through the second transistor.

The invention is mainly directed to providing a charge pump circuit which realizes low power consumption. A first clock signal is supplied from an oscillator circuit to capacitor elements forming a charge pump circuit. A current generation circuit controls a current flowing through each of inverters by controlling operation of PMOS and NMOS, and as a result controls the frequency of the first clock signal. A gate and a drain of PMOS are short-circuited, and between the node thereof and a ground terminal a constant current generation circuit and a resistor are connected in parallel. The constant current generation circuit serves to keep the current flowing through the inverters constant against a change of a power supply voltage. Therefore, the frequency of the clock signal is reduced according to the increase of the power supply voltage.

Charge pump circuit

The invention provides a semiconductor memory device where a circuit area is minimized and a voltage drop in a high voltage supply path to a source line is reduced. An output of a high voltage generation circuit is connected to a source line through a first transfer gate, and connected to a word line through a second transfer gate. The first transfer gate is configured of a P-channel type MOS transistor of which on and off are controlled by a write enable signal, and the second transfer gate is configured of a P-channel type MOS transistor of which on and off are controlled by an erase enable signal. A third transfer gate supplying the output of the high voltage generation circuit to the source line without through a high voltage switching circuit is further provided. The third transfer gate is configured of a P-channel type MOS transistor and an inverted output of the high voltage switching circuit is applied to the gate thereof.

A packaged semiconductor device that enables testing of semiconductor chips incorporated therein in a simplified and efficient manner. The semiconductor device includes a packaged logic chip for processing data and a packaged memory chip for storing data that is processed by or that is to be processed by the logic circuit. The semiconductor device has an automatic rewrite circuit and a selector. The automatic rewrite circuit automatically writes test data to the memory circuit in accordance with a command signal from a tester. The selector selectively switches between accessing of the memory circuit by the automatic rewrite circuit and accessing of the memory circuit by the logic circuit. The tester provides the automatic rewrite circuit with a test start command signal to start testing the logic circuit.

Semiconductor device and method for testing semiconductor device

The present invention provides a memory device including a serial-parallel conversion section that converts serial data into parallel data, a parallel-serial conversion section that converts parallel data into serial data, and a parallel-parallel conversion section that changes a bit width of the parallel data. This memory device connects one external terminal to the serial-parallel conversion section and another external terminal to the parallel-serial conversion section when access using a serial interface is performed. On the other hand, the memory device connects a plurality of external terminals to the parallel-parallel conversion section when access using a parallel interface is performed, thereby enabling the memory device to occasionally realize parallel transfer of data while using a conventional package.

A high speed sense amp supplies current to a bit line connected to a memory cell transistor and also detects a potential of the bit line. The potential of the bit line varies according to a conductive state of the memory cell transistor. The sense amp includes a load element and a first transistor connected in series between a first potential and the bit line. A second transistor is connected between the first potential and the bit line. The bit line is input to an inverter that has its output terminal connected to a gate of the first transistor. A differential amp has a first input terminal connected to a reference potential and a second input terminal connected to a node between the load element and the first transistor. The output of the differential amp indicates a difference between the reference potential and the bit line potential.

Sense amplifier with improved sensitivity

A semiconductor memory device having a reduced circuit area. The semiconductor memory device includes a memory cell array connected to an address decoder, a sense amplifier, a write amplifier, and a command decoder. A first serial/parallel converter is adjacent to the address decoder. A parallel/serial converter is adjacent to the sense amplifier. A second serial/parallel converter is adjacent to the write amplifier. A third serial/parallel converter is adjacent to the command decoder. The serial/parallel converters and the parallel/serial converter are each connected to an input/output circuit via a pair of wires.

Semiconductor memory device including serial/parallel conversion circuit

A write control circuit that generates a control signal to initiate a write operation for a semiconductor memory device, such as an EEPROM, compensates for fluctuations in the supply voltage. The write control circuit includes a control potential generator that produces a first control potential which is kept higher than the ground potential and a second control potential which is kept lower than the supply potential. A first transistor is connected to the supply potential and receives a write potential at its gate. A second transistor is connected between the first transistor and ground and receives the first control potential at its gate. A third transistor is connected to the supply potential and receives the second control potential at its gate. A fourth transistor is connected between the third transistor and ground and receives a potential from a first node between the first and second transistors at its gate. The control signal is generated at a second node between the third and fourth transistors. The control signal is activated when the write potential reaches a certain value.

Write control circuit for semiconductor memory device

A non-volatile semiconductor memory device including a memory cell transistor, a bit line connected to the memory cell transistor, a current controlling element connected between the bit line and a first potential, a dummy cell transistor connected between the bit line and a second potential, and a decoder connected to the memory cell transistor and the dummy cell transistor. The memory cell transistor has an electrically isolated floating gate electrode which varies an on resistance that depends on an amount of charge stored on the floating gate electrode. The decoder, which controls the memory cell transistor and the dummy cell transistor, is operative during a first interval to turn the dummy cell transistor on to apply the second potential to the bit line which is connected to the first potential via said current controlling element and it is operative during a second interval to turn the memory cell transistor on to allow the second potential to be applied to the bit line via the memory cell transistor, thereby allowing a write-in current to pass via the memory cell transistor.

Memory device with dummy cell transistor

An address transition detector (ATD) for a memory device detects a change in an address signal and in response, produces a timing signal. The timing signal is used to align the timing of operation of a memory cell and a sense amp with the timing of the change in the address signal. The ATD includes a detection circuit for detecting a change in the address signal and a transistor having its gate connected to an output of the detection circuit, its source connected to ground and its drain connected to a first input terminal of a logic gate. An output of the logic gate is connected to an inverter. The output of the inverter is connected to a node between the transistor and the first input terminal of the logic gate. The output of the logic gate is also connected to a pair of series connected delay circuits. The output of the second delay circuit is input to a second input terminal of the logic gate. The first delay circuit delays the rising edge of the signal output from the logic gate and the second delay circuit delays the falling edge of the signal output from the logic gate.

Address transition detector for memory device

A word line is connected to a control gate of memory cell transistor, and a bit line and a source line are connected to a drain and a source of the memory cell transistor, respectively. A write clock having a certain crest value is applied to the source line, and an earth potential or a power supply potential is applied to the bit line in response to a read clock having a phase which is opposite to that of the write clock. A row selection clock which synchronizes with the write clock and a crest value of which is de-escalated is applied to the word line.

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Gifu, Japan

Sadao Yoshikawa