Sumitomo Chemical Company, Limited

National Institute of Advanced Industrial Science and Technology

The University of Tokyo

Sadanori Yamanaka

Masahiko Hata

Tomoyuki Takada

Yoshinobu Ono

Yoshihiko Tsuchida

Yasushi Iyechika

Kazumasa Ueda

Taro Itatani

Noboru Fukuhara

Tsuyoshi Nakano

Taketsugu Yamamoto

Naohiro Nishikawa

Hiroyuki Ishii

Kazumi Wada

Masao Shimada

Eiji Kume

Kazuhiko Honjo

Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such as InGaAs, by implanting only a small amount of silicon atoms. Such a semiconductor wafer may include a first semiconductor crystal layer, a second semiconductor crystal layer exhibiting a conductivity type that is different from the first layer, a third semiconductor crystal layer exhibiting the conductivity type of the first layer and having a larger band gap than the second semiconductor crystal layer, and a fourth semiconductor crystal layer exhibiting the conductivity type of the first layer and having a smaller band gap than the third semiconductor crystal layer. The fourth semiconductor crystal layer contains a first element that generates a first carrier of a corresponding conductivity type and a second element that generates a second carrier of a corresponding conductivity type.

Semiconductor wafer, method of producing semiconductor wafer, and heterojunction bipolar transistor

There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SiGe(0&#x2266;x&#x3c;1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.

Semiconductor wafer, semiconductor device, and method of producing semiconductor wafer

There is provided a semiconductor wafer including a base wafer that has an impurity region in which an impurity atom has been introduced into silicon, a plurality of seed bodies provided in contact with the impurity region, and a plurality of compound semiconductors each provided in contact with the corresponding seed bodies and lattice-matched or pseudo-lattice-matched to the corresponding seed bodies. The semiconductor wafer can further include an inhibitor provided on the base wafer and in which a plurality of apertures exposing at least a part of the impurity region are provided.

Semiconductor wafer, electronic device, a method of producing semiconductor wafer, and method of producing electronic device

Electronic device is provided, including: a base wafer whose surface is made of silicon crystal; a Group 3-5 compound semiconductor crystal formed directly or indirectly on partial region of the silicon crystal; an electronic element including a portion of the Group 3-5 compound semiconductor crystal as active layer; an insulating film formed directly or indirectly on the base wafer and covering the electronic element; an electrode formed directly or indirectly on the insulating film; a first coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the electrode; a passive element formed directly or indirectly on the insulating film; a second coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the passive element.

Electronic device and method for producing electronic device

A sensor includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat, where the photothermal absorber outputs an electric signal in response to incident light to be introduced into the photothermal absorber or heat to be applied to the photothermal absorber. A semiconductor wafer includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat.

Sensor, semiconductor wafer, and method of producing semiconductor wafer

The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

Semiconductor wafer, method of producing semiconductor wafer, electronic device, and method of producing electronic device

A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be shaped as an island having a size that does not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal defects when the Ge layer is annealed at a certain temperature.

Semiconductor wafer, semiconductor wafer manufacturing method, and electronic device

A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be formed then annealing with a temperature and duration that enables movement of crystal defects.

Semiconductor wafer including lattice matched or pseudo-lattice matched buffer and GE layers, and electronic device

A semiconductor wafer including: a base wafer; a seed crystal disposed on the base wafer; a compound semiconductor disposed above the seed crystal; and a high resistance layer disposed between the seed crystal and the compound semiconductor, the high resistance layer having a larger resistivity than the seed crystal, and the seed crystal lattice matching or pseudo lattice matching the compound semiconductor is provided.

Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate

A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times.

A method for producing a group 3-5 nitride semiconductor includes the steps of (i), (ii), (iii) in this order: (i) placing inorganic particles on a substrate, (ii) epitaxially growing a semiconductor layer by using the inorganic particles as a mask, and (iii) separating the substrate and the semiconductor layer by irradiating the interface between the substrate and the semiconductor layer with light; and a method for producing a light emitting device further includes adding electrodes.

Method for producing group 3-5 nitride semiconductor and method for producing light-emitting device

Provided is an optical device including a base wafer containing silicon, a plurality of seed crystals disposed on the base wafer, and a plurality of Group 3-5 compound semiconductors lattice-matching or pseudo lattice-matching the plurality of seed crystals. At least one of the Group 3-5 compound semiconductors has a photoelectric semiconductor formed therein, the photoelectric semiconductor including a light emitting semiconductor that emits light in response to a driving current supplied thereto or a light receiving semiconductor that generates a photocurrent in response to light applied thereto, and at least one of the plurality of Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor having the photoelectric semiconductor has a heterojunction transistor formed therein.

Optical device and semiconductor wafer

To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.

Semiconductor wafer, semiconductor device, and method for producing semiconductor wafer

The present invention provides a light emitting device. The light emitting device has a light distribution in which a light distribution I (&#x3b8;, &#x3c6;) obtained when light emitted from a chip of the light emitting device is directly measured is not dependent on a direction &#x3c6; and is substantially represented by I (&#x3b8;, &#x3c6;)=I (&#x3b8;). I (&#x3b8;, &#x3c6;) represents a light intensity distribution in a direction (&#x3b8;, &#x3c6;), &#x3b8; represents an angle from a direction of a normal to a light extraction surface of the light emitting device (0&#x2266;&#x3b8;&#x2266;90&#xb0;), &#x3c6; represents a rotation angle around the normal (0&#x2266;&#x3c6;&#x2266;360&#xb0;), and I (&#x3b8;) represents a monotone decreasing function with which 0 is approached when &#x3b8;=90&#xb0; is satisfied. In the light emitting device, of a structural body constructing the chip of the light emitting device, with regard to a size of a portion of the structural body which is transparent to light emitted from a light emitting layer, a ratio (an aspect ratio) between the size in a lateral direction and the size in a thickness direction is not less than 5 and a structure having a light scattering function is provided on a surface of the light emitting device chip or in an interior of the transparent portion of the structural body.

Light emitting device having a monotone decreasing function

A compound semiconductor luminescent device characterized by comprising an electroconductive substrate, a compound semiconductor function layer including a GaN layer, an electrode, an adhesiveness-enhancing layer, and a bonding layer, which are stacked in this order wherein the above-described electroconductive substrate includes a metal material that indicates a thermal expansion coefficient different by 1.5&#xd7;10&#x2212;6/&#xb0; C. or less from GaN.

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Tsukuba, Japan

Sadanori Yamanaka