Cypress Semiconductor Corporation

S Babar Raza

Somnath Paul

Hagop A Nazarian

M Magdy Talaat

Stephen M Douglass

W Alfred Graf, Iii

Sundar Rajan

Donald A Krall

Shiva Sorooshian Borzin

Darren Duane Neuman

Anup Nayak

Roger J Bettman

Anita X Meng

Walter Francis Bridgewater, Jr

Yun-Che Wang

Dimitris Pantelakis

Michael J Kasper

Edward L Grivna

Mark A Ross

Paul H Scott

Lin-Shih Liu

Steven C Meyers

Donald Y Yu

Christopher S Norris

Khaldoon S Abugharbieh

James B MacArthur

Jiann-Cheng Chen

Darren Newman

Embodiments of the invention are directed to systems and method for providing predictable timing for read operations in a multiport memory device. Accordingly, an embodiment is directed to a multiport memory system, comprising a single port memory core synchronized to a first clock, multiple access ports synchronized to at least a second clock, and a multiplexer logic coupled to the core memory and the plurality of access ports. The multiplexer logic arbitrates access to the memory core between multiple access ports. Each access ports includes an uncertainty detect logic that measures data path latency, and an uncertainty adjust logic that operates to selectively add data path delay to increase the measured path latency to a predictable value.

Logic for implementing a dual clock domain read access with predictable timing for bi-directional inputs/outputs

A device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains is described. In one embodiment, a memory device comprises two or more port synchronization logic devices, a port multiplexing logic, and a single-ported memory core. The port multiplexing logic devices synchronize information communicated between ports associated with the port synchronization logic devices and the single-ported memory core by synchronizing the information between port clocks and a core clock.

Device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains

Embodiments of a method and apparatus for aggregating Ethernet streams are generally described. According to but one example embodiment, implementations of a physical coding sublayer (PCS) modify one or more Ethernet streams to uniquely distinguish at least one of the Ethernet streams from the other Ethernet streams. Any two or more of the modified Ethernet streams may be interleaved to form an aggregate Ethernet stream. The aggregate Ethernet stream may by transmitted over a serial link.

Method and apparatus for aggregating Ethernet streams

A clock detection and selection circuit () can include a first counter (-) that generates a first count value CNTaccording to a first clock signal CLKand a second counter (-) that generates a second count value CNTaccording to a second clock signal CLK. First separation-detect logic (-) and second separation-detect logic (-) determine if a pre-specified difference exists between a first count value (CNT/CNT') and second count value (CNT/CNT&#x2032;). According to such determinations, separation information (INFand INF) can be generated indicating which clock signal (CLKor CLK) is faster. Selection logic () can select a faster of the clock signals (CLKor CLK) if the separation information values confirm one another.

Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.

Method and architecture for synchronizing a path generator and/or extractor to a processor

A memory device, apparatus and method are provided for accessing memory cells. The device, apparatus, and method allow two or more electronic subsystems with corresponding external ports to access a single array of memory elements via a single internal port. Address, data, and control signals from each of the external ports are multiplexed onto the word line drivers and de-multiplexed from the sense amplifiers. Multiplexing and de-multiplexing operations are sequenced based on a state machine that receives synchronized signals from the external port. The synchronized signal can be clock signals that are synchronized to a high-speed sampling clock. Synchronization and sequencing functions can occur over a relatively few number of cycles of the high-speed sampling clock to minimize the time for resolving access conflicts, thereby maximizing the number of external ports which can access the internal port of the array.

System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock

An apparatus configured to extract in-band information or skip extraction of the in-band information and perform a look ahead operation. The apparatus may be configured to switch between the extraction and the skipping of the extraction.

Logic for generating multicast/unicast address (es)

A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred clock speed of a plurality of clock speeds.

Architecture for implementing virtual multiqueue fifos

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a parallel output data signal in response to (i) a first clock signal and (ii) one or more serial data signals. The second circuit may be configured to present the one or more serial data signals and the first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.

Method, architecture and circuitry for controlling pulse width in a phase and/or frequency detector

An apparatus comprising a first logic circuit and a second logic circuit. The first logic circuit may comprise one or more counters and may be configured to synchronize a plurality of input clock signals. The second logic circuit may be configured to detect and present a faster clock signal of the synchronized clock signals.

Configurable fast clock detection logic with programmable resolution

An apparatus for providing arbitration for a dual-port memory. The apparatus may be configured to prevent a write cycle extension during contention between simultaneous read and write operations.

Logic for providing arbitration for synchronous dual-port memory

An apparatus configured to interface a first clock speed of a multiqueue storage device and a second clock speed of an interface. The apparatus may be configured to control a flow of variable size data packets.

FIFO read interface protocol

An apparatus comprising a plurality of storage devices and a scheduler circuit. Each of the plurality of storage devices may be configured to store and present one or more packets of a data stream over one or more first busses operating at a first speed. The scheduler circuit may be configured to determine which of the plurality of storage devices transmits the packets of the data stream. A second bus that may be configured to carry look ahead information and synchronize the plurality of devices. The second bus may operate at a second speed.

Out-of-band look-ahead arbitration method and/or architecture

A method of validating data between a path generator and a path processor, comprising the steps of (A) transmitting validation data from said path generator to said path processor on a data path, (B) sequentially transmitting data on said data path, (C) determining if the transmitted data is valid in response to the validation data and (D) using the overhead data by the processor when the overhead data is validated by the validation data.

Overhead serial communication scheme

The present invention includes a circuit, system, and method for avoiding a non-desired output from a latch, and a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-desired state regardless of the latching input values. The embodiments described herein are useful in forming a non-clocked latch that employs set and reset inputs, and thus, may be an SR latch. The SR latch is envisioned having either MOSFET or bipolar transistors, and can be employed either having only NMOS transistors, only PMOS transistors, or CMOS transistors. The latch also includes an improved selector circuit that is easily programmed to configure the latch in either a set-dominant, a reset-dominant, or a memory-dominant configuration based solely on the voltage values fed to the latch by the selector circuit. As such, the selector circuit of the present invention embodies an improved programmability over previous circuits.

Growing community of inventors

Milpitas, CA, United States of America

S Babar Raza