Hitachi, Ltd.

Renesas Electronics Corporation

Hitachi-high-technologies Corporation

Ryuta Tsuchiya

Toshiaki Iwamatsu

Digh Hisamoto

Nobuyuki Sugii

Takashi Ishigaki

Yusuke Morita

Shinichiro Kimura

Yoshinobu Kimura

Shinichi Saito

Hirofumi Shinohara

Masatada Horiuchi

Hiroyuki Yoshimoto

Kiyoshi Hayashi

Takashi Terada

Naoki Tega

Kozo Ishikawa

Kiyoo Itoh

Takayuki Kawahara

Keiji Watanabe

Toshiyuki Mine

Yusuke Kanno

Satoru Akiyama

Noriyuki Lee

Hiroshi Fukuda

Hiroki Kawada

Yasuhiro Shimamoto

Takashi Hattori

Akio Shima

Yuki Mori

Kazuhiro Mochizuki

Kazuyoshi Torii

Takahiro Onai

Atsuko Yamaguchi

David Arfon Williams

Mieko Matsumura

Akihisa Terano

Yuji Suwa

Takashi Takahama

Tomoko Sekiguchi

Hiroyuki Matsushima

Aleksey Andreev

Tadao Morimoto

Shozo Yoneda

Gou Shinkai

A semiconductor device includes an active region famed in a semiconductor layer formed on an insulating film famed in a semiconductor substrate and having a first extension portion extending in a first direction and a second extension portion extending in a second direction intersecting with the first direction, a first diffusion layer electrode of a first conductivity type provided in the first extension portion, second and third diffusion layer electrodes of a second conductivity type provided in the second extension portion so as to interpose a first connecting portion connecting the first extension portion and the second extension portion, a first gate electrode famed on the first extension portion between the first diffusion layer electrode and the first connecting portion through an insulating film famed on the semiconductor layer, and a second gate electrode famed on the first connecting portion through the insulating film famed on the semiconductor layer.

Semiconductor device comprising plurality of diffusion layer electrodes with different conductivities and gate electrodes

The first layer includes a first gate electrode array disposed in the first direction to control the qubits of the qubit string, and a second gate electrode array disposed in the first direction to control the inter-qubit interaction of the interaction string. The second layer includes a third gate electrode array disposed in the second direction, and a fourth gate electrode array disposed in the second direction adjacently to the third gate electrode array. The third and the fourth gate electrode arrays control a part of the multiple qubits, and a part of the multiple inter-qubit interactions, respectively.

Quantum information processing device

To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at most 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

Semiconductor device and method for controlling semiconductor device

To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

A silicon-based quantum dot device () is disclosed. The device comprises a substrate () and a layer () of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (: FIG.). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers.

Silicon-based quantum dot device

Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layerincludes an n-type resistance relaxation layercovering the bottom portion of the trench, and a p-type field relaxation layer. The p-type field relaxation layeris separated from the trench bottom portion via the resistance relaxation layer, and is wider than the resistance relaxation layer. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.

Silicon carbide semiconductor device and method for producing same

Provided is a vertical MOSFET in which a conduction deterioration phenomenon is prevented during a current return operation and an on-voltage is low during the current return operation. A semiconductor device includes a hole barrier region that is provided between a second-conductivity-type body region and a first-conductivity-type epitaxial layer below a second-conductivity-type body contact region and functions as a potential barrier to a hole which flows from a source electrode to the first-conductivity-type epitaxial layer through the second-conductivity-type body contact region and the second-conductivity-type body region.

Semiconductor device and manufacturing method for same, as well as power conversion device

An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

Semiconductor device and method for manufacturing the same

When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time.

Silicon carbide semiconductor device and manufacturing method thereof

A solar cell including a substrate, a nanopillarhaving diameter Dconnected to the substrate, and a nanopillarhaving diameter Dconnected to the substrateis characterized in that Dis greater than Din order to realize a solar cell having, as the surface structure, a nanopillar array structure with which it is possible to prevent reflection within the broad wavelength region of solar light. A nanopillar array structureformed from two types of nanopillars having different diameters has a point of minimum reflectivity of a nanopillar array structure formed from the nanopillarhaving diameter Dand a point of minimum reflectivity of a nanopillar array structure formed from the nanopillarhaving diameter Dand therefore, is capable of preventing reflection within the broad wavelength region of solar light.

Solar cell

A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.

4h-SiC semiconductor element and semiconductor device

In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mmor more and 28.8 J/mmor less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

Method for manufacturing a solar cell

A semiconductor device includes a nitride semiconductor stack having at least two hetero junction bodies where a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer are disposed, and includes a drain electrode and, a source electrode disposed to the nitride semiconductor stack, and gate electrodes at a position put between the drain electrode and the source electrode and disposed so as to oppose them respectively in which the drain electrode and the source electrode are disposed over the surface or on the lateral side of the nitride semiconductor stack, and the gate electrode has a first gate electrode disposed in the direction of the depth of the nitride semiconductor stack and a second gate electrode disposed in the direction of the depth of the nitride semiconductor at a depth different from the first gate electrode.

Semiconductor device with hetero-junction bodies

Growing community of inventors

Tokyo, Japan

Ryuta Tsuchiya