Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Ryuichi Izawa

Masakazu Aoki

Iwao Takemoto

Masaharu Kubo

Shinya Ohba

Haruhisa Ando

Masaaki Nakai

Shoji Hanamura

Kazuo Yano

Mitsuru Hiraki

Masataka Minami

Tokuo Kure

Atsuo Watanabe

Takahiro Nagano

Atsushi Hiraiwa

Kenji Takahashi

Norio Koike

Kazushige Sato

Keiichi Yoshizumi

Eiji Takeda

Toshifumi Ozaki

Shuhei Tanaka

Shimpei Iijima

Kouichi Seki

Yasuo Igura

Akemi Hamada

Syoji Hanamura

A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.

Gate circuit, semiconductor integrated circuit device and method of

Herein disclosed is a semiconductor device of high density. The semiconductor device having a high density and a microstructure is required to have a high breakdown voltage and a high speed even with a low supply voltage. The semiconductor device comprises: a semiconductor body; a gate insulating film formed over the body; and a MOS transistor having a source/drain region formed in the body and a gate electrode film formed over the gate insulating film. The gate electrode film is composed of two or more films having different etching rates. The gate etching is stopped at the interface of the composite film to form an inverse-T gate electrode structure; and in that an electric conduction is observed between the component films. Thus, the overlap between the gate and the drain can be controlled.

Transistor with overlapping gate/drain and two-layered gate structures

In a solid-state imaging device having a plurality of photodiodes which are arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements and a group of vertical switching elements which pick up the photodiodes, and a horizontal scanning circuit and a vertical scanning circuit which impress scanning pulses on the horizontal and vertical switching elements respectively, and having an interlaced scanning mechanism which picks up a plurality of vertical scanning lines by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows; a solid-state imaging device characterized in that said interlaced scanning mechanism includes insulated-gate field effect transistors for recovering voltage levels of the scanning pulses having undergone voltage drops due to the interlace switching elements.

Interlaced solid-state imaging device

A solid-state imaging device wherein a MOS sensor is employed for a photosensor part, a CTD shift register is employed for a read-out circuit, first and second transfer gates are connected between vertical signal output lines and the CTD, and a reset gate is connected between a juncture of the first and second transfer gates and a reset voltage line. A method is adopted in which signal outputs of a plurality of rows are transferred to the CTD in a horizontal blanking period, and signals of a plurality of rows are simultaneously read out in a horizontal scanning period. At the signal transfer, bias charges are dumped into the vertical signal output lines from the CTD, and mixed charges consisting of the bias charges and signal charges are transferred to the CTD. Thereafter, the signals are read out.

Solid-state imaging device

In a solid-state imaging device having in one major surface region of a monolithic semiconductor body, photodiodes which are arrayed in two dimensions, vertical switching MOS transistors and horizontal switching MOS transistors which address the photodiodes, MOS transistors which constitute vertical and horizontal scanning circuits for turning 'on' and 'off' the switching MOS transistors, and MOS transistors which constitute other peripheral circuitry, the photodiodes being constructed of source regions of the vertical switching MOS transistors and the semiconductor body; a solid-state imaging device characterized in that among source and drain regions of the various MOS transistors, the source regions of the vertical switching MOS transistors are lower in the surface impurity concentration and deeper in the junction depth than the other source and drain regions.

A circuit for generating scanning pulses comprising a plurality of stages of basic circuits connected in series, said each basic circuit comprising first, second and third insulated gate field-effect transistors (MISTs) each of which has first and second terminals each being either of source and drain terminals and a gate terminal, said first terminal of said first MIST being used as a clock pulse-applying terminal, said gate terminal of said first MIST being used as an input terminal, said second terminal of said first MIST and said first terminal and said gate terminal of said second MIST being connected and used as a scanning pulse output terminal, said second terminal of said second MIST and said first terminal of said third MIST being connected and used as an output terminal, said second terminal of said third MIST being used as a ground terminal, said gate terminal of said third MIST being used as a feedback input terminal.

Circuit for generating scanning pulses

Growing community of inventors

Kokubunji, Japan

Ryuichi Izawa