Globalfoundries Inc.

Tessera Advanced Technologies, Inc.

Ryoung-Han Kim

Matthew Earl Colburn

A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor M, upper conductor M, dielectric interlayer (DIL) and interconnecting via conductor V. The lower conductor Mhas a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor M, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor Mand the connecting via conductor Vmaking electrical contact with the first upper surface. A critical dimension between others of lower conductors Mand the via conductor Vis lengthened. Leakage current and electro-migration therebetween are reduced.

Multilayer interconnect structure and method for integrated circuits

A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor M, upper conductor M, dielectric interlayer (DIL) and interconnecting via conductor V. The lower conductor Mhas a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor M, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor Mand the connecting via conductor Vmaking electrical contact with the first upper surface. A critical dimension between others of lower conductors Mand the via conductor Vis lengthened. Leakage current and electro-migration there-between are reduced.

A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions. Embodiments further include using a third mask to form a semiconductor device having further features with a different critical dimension, but the same pitch, as the sub-resolution features.

Spacer double patterning that prints multiple CD in front-end-of-line

A method for forming an interconnect structure includes forming a mandrel above a base layer, forming spacers on the mandrel, forming recesses in the base layer using the spacers as an etch template, and forming a conductive material in the recesses.

Method for forming an interconnect structure

Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In one embodiment, a method comprises the steps of forming etch masking features overlying the semiconductor substrate, the etch masking features having a first thickness, and forming an etch barrier layer overlying the substrate, the etch barrier layer having a second thickness less than or substantially equal to the first thickness. The method also comprises removing the etch masking features to expose the substrate, and etching the substrate using the etch barrier layer as an etch mask.

Growing community of inventors

Clifton Park, NY, United States of America

Ryoung-Han Kim