Fujitsu Corporation

Vlsi Technology Research Association

Ryoiku Togei

Kunihiko Wada

Akira Takei

Yoshihiko Hika

A non-volatile memory device which stores data by capturing charges in an amorphous semiconductor layer. The amorphous semiconductor layer is provided between a gate electrode and a semiconductor substrate via an insulating film and its edge is in contact with at least the one of the source or drain electrodes in the semiconductor substrate. When a high voltage (10 V or higher) is applied to the gate electrode, an electric field is generated and thereby charges are injected into the amorphous semiconductor layer from the source and/or drain electrode and a write operation is thus carried out. An erasing operation is carried out by injection of charges of inverse polarity. This memory device offers advantages of low operating voltage and excellent charge sustaining characteristic, resulting from the fact that the write operation is attained independently of the gate insulating film.

Non-volatile semiconductor memory device

The capacity of a capacitor constituted by a metal-insulator-semiconductor layer configuration varies depending on the quantity of electric charge staying in the neighborhood of the interface between the insulating layer and the semiconductor layer. Because interleaving of a thin semiconductor layer between the insulating layer and the semiconductor layer to form a P-N junction therebetween is effective to confine some quantity of electric charge in the thin semiconductor layer, the capacity of the capacitor can be regulated. When the quantity of electric charge confined in the thin semiconductor layer is given in the form of an electric pulse signal, the signal can be memorized in the form of capacity. A layer configuration of a conductor, an insulator and a semiconductor, including a P-N junction therein fabricated on a substrate with which the layers are isolated, functions as a memory cell which consists of only one capacitor and, which requires an extremely small area of a chip, and which is involved with non destructive read out. The same layer configuration is effective to function as a photoelectro transducer or an image sensor unit, when the conductor layer is fabricated with a transparent conductor.

Semiconductor device

Disclosed herein is a semiconductor memory device comprising a semiconductor substrate having a first conductivity type, first and second regions of a second conductivity type opposite to said first type formed in the surface of the semiconductor substrate and separated with a certain space therebetween, a third region of the first conductivity type formed in the second region, and a gate electrode formed on an insulating film on the semiconductor substrate between the first and the third regions. By applying a gate voltage to the gate electrode, charge carriers are transferred between the first and second regions in accordance with the data to be stored. The stored data is read out by applying a prescribed gate voltage to the gate electrode and by detecting the value of the current between the third region and the semiconductor substrate.

Complementary semiconductor memory device

A method of producing a semiconductor device comprises a step of forming a field isolating oxide layer from an amorphous silicon layer by oxidation at a relatively low temperature. Prior to the oxidizing treatment, a portion of the amorphous silicon layer is recrystallized into a single-crystalline silicon layer by laser irradiation.

Method of producing semiconductor devices by selective laser irradiation

Disclosed herein is a small-sized semiconductor memory device, wherein an N.sup.+ (P.sup.+)-type single region having an input function and an output function and an electrode for controlling the electrical potential in a P(N)-type Si substrate are provided on the top surface of the P(N)-type Si substrate. In order to store carriers, i.e., an information, in the bulk of the substrate, an N (P)-type buried layer is formed below the N.sup.+ (P.sup.+)-type input-output region, mentioned above. Information is quickly transferred from or into the buried layer by means of the punch-through effect, which is realized by spreading a depletion layer formed at a PN junction between the input-output region and the Si substrate. Since the carriers are stored in the bulk of the substrate, the size of the memory device is reduced and the surface property of the device does not exert a harmful influence on the carriers.

Semiconductor memory device

On a semiconductor substrate (or layer) of one conductivity type, a semiconductor layer of the opposite conductivity type is formed and a source and a drain region of the same conductivity type as the semiconductor substrate are formed in the semiconductor layer. Junctions are respectively formed between the source and drain regions and the semiconductor layer at such positions where punch-through may easily occur between the source and drain regions and the semiconductor substrate when operating voltages are applied to these regions. A local potential distribution generation electrode, which makes an ohmic contact with the semiconductor layer, is formed between the source and drain regions. By applying voltages to both the local potential distribution generation electrode and a drain electrode at substantially the same time, a potential barrier normally formed in the semiconductor layer is removed, thereby to inject carriers from the source region to the drain region through the semiconductor substrate (or layer).

A semiconductor memory device, which comprises: a P-type semiconductor material comprising on the surface thereof, an N-type doped layer, one surface region of the substrate adjoining the doped layer being used as a gate region, and further comprising in the interior thereof an N-type buried layer below another surface region of said substrate adjoining said one surface region. Electric charges representing information are stored in the buried layer. The reading time and the refreshing period are improved by shortening said reading time and lengthening said refreshing time utilization of said N-type buried layer.

A semiconductor memory device provided with one transferring electrode, one gate electrode and one diode of a charge coupled device is produced by a process with a reduced number of steps of diffusion and patterning. Both electrodes consists of doped polycrystalline silicon and both are electrically connected to a resistive layer which consists of non-doped polycrystalline silicon. A potential barrier between the region of both electrodes is removed due to the resistive layer. Resistive layer is formed by utilization of a two-stage deposition of the polycrystalline silicon layer with appropriate mashing steps.

A semiconductor memory device provided with one transferring electrode, one gate electrode and one diode of a charge coupled device is produced by a process with a reduced number of steps of diffusion and patterning. Both electrodes consist of doped polycrystalline silicon and both are electrically connected to a resistive layer which consists of non-doped polycrystalline silicon. A potential barrier between the region of both electrodes is removed due to the resistive layer. The resistive layer is formed by utilization of a two stage deposition of the polycrystalline silicon layer with appropriate masking steps.

Growing community of inventors

Machida, Japan

Ryoiku Togei