Other

Elpida Memory, Inc.

Hitachi, Ltd.

Nec Corporation

Ryoichi Nakamura

Satoru Yamada

Ryo Nagai

Yoshitaka Nakamura

Norikatsu Takaura

Kiyonori Oyu

Shigetomi Michimata

A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a pdiffused region; implanting indium into the surface of the pdiffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.

Semiconductor device and method of manufacturing the same

In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

Hybrid semiconductor device having an n+ (p) doped n-type gate and method of producing the same

It is intended to enable simultaneous formation of concave capacitor storage electrodes and a convex bit contact plug electrode and thereby makes it possible to reduce spaces of margins for alignment errors by decreasing the number of lithography steps. Gate electrodes are formed on a p-well in such a manner that the gate electrode interval in storage electrode forming portions is longer than that in a bit contact plug forming portion, and sidewalls are then formed. An SiO film is deposited, storage electrode forming holes and a bit contact plug forming holes are formed therein, and then a polysilicon film is deposited. Another SiO film is deposited on the polysilicon film and etched back. Then, the polysilicon film is etched back. After etching of the SiO films, capacitor insulating films and counter electrodes are formed and a bit line is also formed.

Semiconductor device having concave electrode and convex electrode and method of manufacturing thereof

A semiconductor device is disclosed including an insulated gate field effect transistor (IGFET) having a gate insulating layer ( ), a gate electrode ( ), and a source-drain layer ( ). The IGFET may include a bird's beak insulating film ( ) in a region in which the gate insulating layer ( ) overlaps the source-drain layer ( ). The bird's beak insulating film ( ) may have a thickness that is greater than the gate insulating film ( ). In this way, inter-band tunneling may be reduced. A plurality of IGFETs may include bird's beak insulating films having different configurations in accordance with operating conditions of the circuit in which the particular IGFET is included.

Semiconductor device and method for its manufacture

A semiconductor device of the present invention has a plurality of capacitors having a cylindrical lower electrode which is formed along the side and the bottom surface of a recess formed in an insulator film over a semiconductor substrate and which is made of silicon having a lot of grained silicon on the surface, and a protector film with resistance to etching of a silicon oxide film is formed at least on the upper surface of the insulator film positioned between the adjacent lower electrodes.

Semiconductor memory device and manufacturing method thereof

The thickness of the silicon oxide film covering the upper surface of the word lines 111 is thinner than the thickness of the insulation film spacer 127a covering the side of the gate electrode, and in reflection of this phenomenon, the step of the upper surface of the BPSG film 133 becomes smaller than 1/2 of the depth of focus DOF of the KrF excimer laser and bit lines 137a are formed which have a narrower width and interval than the wavelength of the KrF excimer laser free from the disconnection and the short circuit. As a consequence, bit lines have narrower widths and interval than the wavelength of the exposure light without sacrificing the productivity.

Growing community of inventors

Tokyo, Japan

Ryoichi Nakamura