Globalfoundries Inc.

Ryan Ryoung-Han Kim

Ruilong Xie

Lei Sun

William James Taylor, Jr

Kwan-Yong Lim

Wenhui Wang

Linus Jang

Min Gyu Sung

Youngtag Woo

Jason Cantone

Chanro Park

Xunyuan Zhang

Seowoo Nam

Yulu Chen

Erik A Verduijn

Jongwook Kye

Andy C Wei

John A Iacoponi

Azat M Latypov

Deepak K Nayak

Andre P Labonte

Tamer Coskun

Jin Haeng Cho

Motoi Ichihashi

Myungjun Lee

A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PUand PU) transistors, and first and second pull-down (PDand PD) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PUand PU. A second bottom electrode connects bottom SD regions of PDand PD. A first shared contact connects the top SD region of PUto the gate structure of PU. A second shared contact connects the top SD region of PDto the gate structure of PD. A first top electrode is connected to the top SD regions of PG, PUand the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG, PUand the first shared contact to define a second storage node of the memory cell.

Vertical transistor static random access memory cell

Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Dummy gate used as interconnection and method of making the same

A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

Method of utilizing trench silicide in a gate cross-couple construct

Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

Shrink process aware assist features

In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting.

Semiconductor device configured for avoiding electrical shorting

A method includes providing a structure having a dielectric layer, a 1hardmask layer, a 2hardmask layer and a 1mandrel layer disposed respectively thereon. A 1mandrel plug is disposed in the 1st mandrel layer. A 2mandrel layer is disposed over the 1mandrel layer. The 1and 2mandrel layers are etched to form a plurality 1st mandrels, wherein the 1mandrel plug extends entirely through a single 1mandrel. The 1mandrel plug is etched such that it is self-aligned with sidewalls of the single 1mandrel. The 1mandrels are utilized to form mandrel metal lines in the dielectric layer. The 1mandrel plug is utilized to form a self-aligned mandrel continuity cut in a single mandrel metal line formed by the single 1mandrel.

Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines

One illustrative integrated circuit product disclosed herein includes, among other things, a plurality of FinFET devices, each of which comprises a gate structure comprising a high-k gate insulation material and at least one layer of metal, a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, the SDB isolation structure comprising the high-k insulating material and the at least one layer of metal, and a double diffusion break (DDB) isolation structure positioned in a second trench defined in a semiconductor substrate between third and fourth active regions, the DDB isolation structure comprising a first insulating material that substantially fills the second trench.

Single and double diffusion breaks on integrated circuit products comprised of FinFET devices

A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.

Vertical channel transistor-based semiconductor memory structure

A method of optical proximity correction (OPC) in extreme ultraviolet lithography (EUV) lithography includes providing a patterned layout design including first and second design polygons that correspond with the pre-pattern opening, wherein the first and second design polygons are separated by a separation distance, and correcting the patterned layout design using OPC by generating (1) a third polygon that has dimensions corresponding to a combination of the first and second design polygons and the separation distance and (2) and filled polygon within the third polygon, thereby generating an OPC-corrected patterned layout design. EUV photomasks may be manufactured from the OPC-corrected patterned layout design, and integrated circuits may be fabricated using such EUV photomasks.

Methods for optical proximity correction in the design and fabrication of integrated circuits using extreme ultraviolet lithography

A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.

Methods of forming reduced resistance local interconnect structures and the resulting devices

One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second plurality of fins in the second region of the substrate, and a space in the substrate between two adjacent fins in the second region that corresponds to a first isolation region to be formed in the second region, forming a fin removal masking layer above the first and second regions of the substrate, wherein the fin removal masking layer has an opening positioned above at least a portion of at least one of the first plurality of fins, while masking all of the second plurality of fins in the second region and the space for the first isolation region, and performing an etching process through the first opening to remove the portions of the at least one of the first plurality of fins.

Methods of forming products with FinFET semiconductor devices without removing fins in certain areas of the product

There is set forth herein a gate contact structure for a gate. The gate contact structure can include a first contact layer and a second contact layer. In one embodiment, a gate contact layer can define a contact that provides a gate tie down. In one embodiment, a gate contact layer can have a minimum width larger than a gate length.

Growing community of inventors

Albany, NY, United States of America

Ryan Ryoung-Han Kim