International Business Machines Corporation

Globalfoundries Inc.

Ryan O Jung

Kangguo Cheng

Fee Li Lie

John Ryan Sporre

Sean Teehan

Ruilong Xie

Andrew Mark Greene

Jeffrey C Shearer

Eric R Miller

Sivananda K Kanakasabapathy

Alexander Reznicek

Peng Xu

Soon-Cheon Seo

Sanjay C Mehta

Marc Adam Bergendahl

Yunpeng Yin

James John Kelly

James J Demarest

Linus Jang

Alex Richard Hubbard

Richard A Johnson

Allan Ward Upham

Tenko Yamashita

Steven J Bentley

Sean David Burns

Chia-Yu Chen

Shyng-Tsong Chen

Michael John Hargrove

Allen H Gabor

Neal V Lafferty

Sivanandha K Kanakasabapathy

Sudharshanan Raghunathan

Erin Catherine McLellan

A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

Gate cut with high selectivity to preserve interlevel dielectric layer

Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.

Method and structure for enabling high aspect ratio sacrificial gates

A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.

Method and structure for enabling controlled spacer RIE

A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins.

Method to form dual channel semiconductor material fins

A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

Trench formation for dielectric filled cut region

Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

Junction overlap control in a semiconductor device using a sacrificial spacer layer

A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask.

Methods of patterning features having differing widths

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Rensselaer, NY, United States of America

Ryan O Jung