Tokyo Electron Limited

The University of Texas System

Ryan Burns

Mark H Somervell

William John Koros

Michael Carcasi

Benjamen M Rathsack

Makoto Muramatsu

Corey Lemley

In certain embodiments, a method for processing a substrate includes applying a surface treatment to selected surfaces of the substrate. The substrate has a non-planar topography including structures defining recesses. The method further includes depositing a fill material on the substrate by spin-on deposition. The surface treatment directs the fill material to the recesses and away from the selected surfaces to fill the recesses with the fill material without adhering to the selected surfaces. The method further includes removing the surface treatment from the selected surfaces of the substrate and depositing a planarizing film on the substrate by spin-on deposition. The planarizing film is deposited on the selected surfaces and top surfaces of the fill material.

Planarization of semiconductor devices

Methods used to more accurately predict spin on layer planarization over a patterned topography are provided. Methods are provided for generating a layer critical dimension model. In one embodiment, the critical dimension model is a layer thickness model that more accurately simulates patterned topography trends, as a function of feature dimensions, surrounding pattern density and radial position across the patterned topography. Additional methods are provided for calibrating the layer thickness model over one or more spatial areas to account for radial variations in the patterned topography. Further methods are provided for using one or more calibrated layer thickness models to predict a thickness of a layer (e.g., a spin on coating) as it is being deposited onto a patterned substrate. The methods disclosed herein may facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar layer or layer on the substrate.

Predicting across wafer spin-on planarization over a patterned topography

Described herein are technologies to facilitate device fabrication, especially those that involve spin coatings of a substrate. More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

System and method of planarization control using a cross-linkable material

Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Facilitation of spin-coat planarization over feature topography during substrate fabrication

A polymeric composite may be used for forming fluid separation membranes. The fluid separation membranes may go through a separation selectivity maximum as a function of operating conditions (e.g., temperature and/or pressure). The membranes may be formed from polyamide or poly (pyrrolone-imide). Polyamides may be formed by the condensation of a tetraamine, a tetraacid, and a diamine. Poly (pyrrolone-imides) may be formed by the condensation of a polyamide.

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Austin, TX, United States of America

Ryan Burns