Intel Corporation

California Institute of Technology

Ruth Amy Brain

Charles Henry Wallace

Mohit K Haran

Mark T Bohr

Florian Gstrein

Rami Hourani

Tejaswi K Indukuri

Flavio Griggio

Marvin Young Paik

Yuriy V Shusterman

Yih Wang

Marie Krysak

Makarem A Hussein

Kevin Fischer

Reken Patel

Michael A Childs

Debashish Basu

Hyunsoo Park

Ian A Young

Uygar E Avci

Valery M Dubin

Harry A Atwater

Michael L Hattendorf

Manish Chandhok

Seiyon Kim

Christopher P Auth

Daniel Henry Morris

Kevin J Lee

Sean W King

Andrew W Yeoh

Jason W Klaus

Martin B Barmatz

Chin-Chang Cheng

Ranjith Kumar

James Jeong

Phi L Nguyen

Alexander F Kaplan

Deepak S Rao

Seungdo An

Kilhyun Bang

Daniel James Bahr

Tahir Ghani

Oleg Golonzka

Alan M Myers

Richard E Schenker

Paul Anton Nyhus

Eungnak Han

Kanwal Jit Singh

Jasmeet S Chawla

Curtis W Ward

Christopher M Pelto

Sam Sivakumar

Chi-Hwa Tsang

Marni Nabors

Sukru Yemenicioglu

Martin Weiss

Jick M Yu

Sourav Chakravarty

Shannon Daviess

Gerald S Leatherman

Harshitha Vishwanath

Tai-Hsuan Wu

Bob Bigwood

Robert Turklot

Renukprasad Hiremath

Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in a trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.

Plug and trench architectures for integrated circuits and methods of manufacture

Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate, and a cell on the substrate. In an embodiment, the cell comprises a plurality of transistors over the substrate, and a first metal layer over the plurality of transistors. In an embodiment, the first metal layer comprises a first power line, wherein a width of the first power line is entirely within the cell, a second power line, wherein a width of the second power line is entirely within the cell, and a plurality of signal lines between the first power line and the second power line.

Metal space centered standard cell architecture to enable higher cell density

Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

Replacement metal COB integration process for embedded DRAM

An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

Via contact patterning method to increase edge placement error margin

Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

Conductive cap-based approaches for conductive via fabrication and structures resulting therefrom

Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces.

Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded SRAM in state-of-the-art CMOS technology

Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.

Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.

Conductive via and metal line end fabrication and structures resulting therefrom

An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

Power shared cell architecture

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.

Etch-stop layer topography for advanced integrated circuit structure fabrication

Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

Decoupled via fill

Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory

Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

Via blocking layer

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Portland, OR, United States of America

Ruth Amy Brain