Micron Technology Incorporated

Round Rock Research, LLC

Other

Russell C Zahorik

Guy F Hudson

Brian F Gordon

Todd A Dobson

Alan R Reinberg

Brenda D Kraus

John H Givens

Hugh E Stroupe

Fernando N Gonzalez

Graham Richard Wolstenholme

Scott G Meikle

Everett Allen McTeer

Randhir P Thakur

Robert James Burke

Paul A Paduano

Timothy P O'Brien

Thomas N Melody

John E Knudson

Leslie A Pearey

Hugh F Stroupe

A device with a memory array is disclosed. In one embodiment, the memory array includes a plurality of memory cells, each including an electrode and a phase change material. The electrode may be disposed on a substrate, the electrode having a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode.

Phase change memory cell and devices containing same

A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.

Apparatus and methods for selective removal of material from wafer alignment marks

A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided.

Method of fabricating phase change memory cell

Small electrode for phase change memories

A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is substantially circular and an exposed surface that has a sublithographic dimension in a direction parallel to the exposed surface. Further, the method may also include forming a layer of phase change material coupled to the exposed surface of the electrode. Various semiconductor devices and additional methods of manufacturing memory cells are also provided.

A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes are formed. The electrodes thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

Method of fabricating a conductive path in a semiconductor device

A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is disclosed with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment is used to form a metal silicide contact at the bottom of the contact hole upon a semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited within the recess.

Semiconductor device with metal fill by treatment of mobility layers including forming a refractory metal nitride using TMEDT

Apparatus for selective removal of material from wafer alignment marks

A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment is used to form a metal silicide contact at the bottom of the contact hole upon a semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited within the recess. High pressure and temperature are used to substantially fill the recess with the metallization layer. Following the substantially filling of the recess, residual surface metallization may at least be partially removed by techniques such as etch back or CMP.

Method for metal fill by treatment of mobility layers

Method of fabricating a small electrode for chalcogenide memory cells

A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.

X-point memory cell

Titanium aluminum nitrogen (&ldquo;Ti&mdash;Al&mdash;N&rdquo;) is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti&mdash;Al&mdash;N layer serves as a cap layer which prevents unwanted reflection of photolithography light (i.e., photons) during fabrication. For field emission display devices (FEDs), the Ti&mdash;Al&mdash;N layer prevents light originating at the display screen anode from penetrating transistor junctions that would hinder device operation. For the wiring line embodiment an aluminum conductive layer and a titanium-aluminum underlayer are formed beneath the antireflective cap layer. The Ti&mdash;Al underlayer reduces the shrinkage which occurs in the aluminum conductive layer during heat treatment.

Antireflective coating and field emission display device, semiconductor device and wiring line comprising same

An ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally. The ultra-small electrode is fabricated by a technique in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes are formed. The electrodes thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

Small electrode for chalcogenide memories

Methods for selective removal of material from wafer alignment marks

A method for manufacturing a memory device having a plurality of memory cells. Each memory cell has a non-volatile resistive memory element with a small active area. A plurality of memory cells are formed at selected locations of at least a portion of a semiconductor wafer. To form the memory cells, a lower electrode layer and a memory material layer are deposited over at least a portion of the wafer. Patterns are formed over desired contact locations of the memory material layer and etching is used to remove portions of the memory material layer. The etching step undercuts the patterns and forms memory elements having a protruding contact portion with an apex contact area. The pattern is removed, and an upper electrode is formed and electrically coupled to the contact area. Corresponding access devices and word/bit line conductor grids are provided and coupled to the memory cells.

Growing community of inventors

Boise, ID, United States of America

Russell C Zahorik