International Business Machines Corporation

Globalfoundries Inc.

Ulvac, Inc.

Elpis Technologies Inc.

Ruqiang Bao

Choonghyun Lee

Hemanth Jagannathan

Dechao Guo

Junli Wang

Vijay Narayanan

Shogo Mochizuki

Siddarth A Krishnan

Unoh Kwon

Heng Wu

Zhenxing Bi

Paul Charles Jamison

Kangguo Cheng

Brent A Anderson

Zheng Xu

Gen Tsutsui

Andrew Mark Greene

Huimei Zhou

Reinaldo Ariel Vega

Lan Yu

Takashi Ando

Terence B Hook

Koji Watanabe

Robert Russell Robison

Chun Wing Yeung

Indira P Seshadri

Michael P Belyansky

Derrick Liu

Michael A Guillorn

Keith Kwong Hon Wong

Sivananda K Kanakasabapathy

Jing Guo

Ruilong Xie

Tenko Yamashita

Ekmini Anuja De Silva

Nicolas J Loubet

Julien Frougier

Jingyun Zhang

Zuoguang Liu

Rajasekhar Venigalla

David Lee Rath

Kisup Chung

Lawrence Alfred Clevenger

Michael Rizzolo

Benjamin David Briggs

Koichi Motoyama

Nelson M Felix

Muthumanickam Sankarapandian

Cornelius Brown Peethala

Nicole A Saulnier

Kai Zhao

Siva Kanakasabapathy

Devendra K Sadana

Pouya Hashemi

Stephen W Bedell

Chen Zhang

Oleg Gluschenkov

Balasubramanian Pranatharthiharan

Injo Ok

Joel Pereira De Souza

Sanjay C Mehta

Su Chen Fan

Yann Mignot

Andrew Herbert Simon

Hosadurga K Shobha

Gauri V Karve

Kevin W Brew

Dongbing Shao

Yongan Xu

John Rozen

Joe Lee

Adra Carr

Marinus Hopstaken

Gangadhara Raja Muthinti

Iqbal Rashid Saraf

Yohei Ogawa

Masanobu Hatanaka

Juntao Li

Veeraraghavan S Basker

Peng Xu

Xin Miao

Chanro Park

Son Van Nguyen

Min Gyu Sung

Ravikumar Ramachandran

John Anthony Fitzsimmons

Huiming Bu

Eric R Miller

Barry P Linder

Shahab Siddiqui

Rishikesh Krishnan

Albert M Young

Qianwen Chen

Miaomiao Wang

Pietro Montanini

Tsung-Sheng Kang

Ernest Y Wu

Hung H Tran

Sagarika Mukesh

Prasad Bhosale

Semiconductor devices and methods of forming the same include a first transistor in a first region having a first work function metal layer. A second transistor in a second region has a second work function metal layer that overlaps a portion of the first work function metal layer and that has a vertical part above the portion of the first work function metal layer.

Non-overlapping gate conductors for GAA transistors

A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.

Stacked field effect transistor structure with independent gate control between top and bottom gates

A semiconductor device includes a substrate; a set of first transistors positioned on an upper surface of the substrate, each of the set of first transistors comprising a first gate and a first dielectric; an insulating layer positioned on an upper surface of the set of first transistors; and a set of second transistors positioned over the set of first transistors and with the set of first transistors on an upper surface of the insulating layer, each of the set of second transistors having a second gate and a second dielectric; wherein each of the first dielectrics is connected to a sidewall of each of a corresponding first gate; and wherein each of the second dielectrics is connected to the insulating layer.

Multi-VT solution for replacement metal gate bonded stacked FET

A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

Stacked FETS including devices with thick gate oxide

A semiconductor structure may include one or more nanosheet field-effect transistors formed on a first portion of a substrate, and one or more fin field-effect transistors formed on a second portion of the substrate. A source drain of the one or more nanosheet field-effect transistors or a gate of the one or more nanosheet field-effect transistors may be separated from the substrate by an isolation layer. A source drain of the one or more fin field-effect transistors or a gate of the one or more fin field-effect transistors may be in direct contact with the substrate. The semiconductor structure may include a gate spacer surrounding the gate of the one or more nanosheet field-effect transistors and the gate of the one or more fin field-effect transistors.

Gate-all-around nanosheet field effect transistor integrated with fin field effect transistor

Embodiments of the invention include a dielectric reflow technique for boundary control in which a first layer is deposited on a first transistor region and a second transistor region, the first and second transistor regions being adjacent. A dielectric layer is formed to protect the second transistor region such that the first transistor region is exposed, the dielectric layer bounded at a first location. In response to removing a portion of the first layer on the first transistor region, the dielectric layer protecting the second transistor region is reflowed such that at least a reflowed portion of the dielectric layer extends beyond the first location.

Dielectric reflow for boundary control

A field effect device is provided. The field effect device includes a lower active gate structure on a substrate, and a first lower source/drain on a first side of the lower active gate structure. The field effect device further includes a second lower source/drain on a second side of the lower active gate structure opposite the first side, and a first lower source/drain contact interface on the first lower source/drain. The field effect device further includes a first upper source/drain on the first side of an upper active gate structure, and a second upper source/drain on the second side of the upper active gate structure opposite the first side. The field effect device further a shared source/drain contact forming an electrical connection between the first lower source/drain and the first upper source/drain; and a lower source/drain contact forming an electrical connection to the second lower source/drain.

Middle of line structure with stacked devices

A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

Stacked FETS with non-shared work function metals

Embodiments of present invention provide a method of forming a transistor structure. The method includes receiving a first and a second gate region of a first and a second transistor, the second transistor being adjacent to the first transistor; forming a first work-function metal surrounding the first gate region; truncating the first work-function metal at a first boundary between the first transistor and the second transistor; forming one or more work-function metals surrounding the first gate region; truncating the one or more work-function metals at a second boundary between the first boundary and the second transistor; and forming another work-function metal surround the first and second gate regions. A transistor structure formed thereby is also provided.

Metal gate boundary for transistor scaling

A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets (NS) and a method of forming such a structure. The structure is a three dimensional (3D) integration by vertically stacking nFETs and pFETs for area scaling. In an embodiment, vertically-stacked NS FET structures include a first nanosheet transistor located above a second nanosheet transistor; the first nanosheet transistor including a first NS channel material, wherein the first NS channel material includes a first crystalline orientation; the second nanosheet transistor including a second NS channel material, wherein the second NS channel material comprises a second crystalline orientation, the first crystalline orientation is different from the second crystalline orientation. In an embodiment, each of the respective formed vertically-stacked NS FET structures include respective suspended stack of nanosheet channels that are self-aligned with each other.

Self-aligned hybrid substrate stacked gate-all-around transistors

A method includes forming a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and forming a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region. The second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers vertically stacked over the second region. An encapsulation layer is epitaxially grown along sidewalls of the alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers, and an oxide layer is formed in contact with a top surface of an uppermost second semiconductor channel layer of the alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers and in contact with opposite sidewalls of the encapsulation layer.

Sidewall epitaxy encapsulation for nanosheet I/O device

A stacked FET structure having independently tuned gate lengths is provided to maximize the benefit of each FET within the stacked FET structure. Notably, a vertically stacked FET structure is provided in which a bottom FET has a different gate length than a top FET. In some embodiments, a dielectric spacer can be present laterally adjacent to the bottom FET and the top FET. In such an embodiment, the dielectric spacer can have a first portion that is located laterally adjacent to the bottom FET that has a different thickness than a second portion of the dielectric spacer that is located laterally adjacent the top FET.

Independent gate length tunability for stacked transistors

A semiconductor structure includes a common semiconductor substrate; a first field effect transistor (FET) gate formed on the substrate, which has a first threshold voltage and comprises a first work function metal and a first barrier layer, and a second FET gate formed on the substrate, which has a second threshold voltage and comprises the first work function metal, the first barrier layer, and a second work function metal.

Multiple threshold voltage scheme in complementary metal oxide semiconductor transistors

A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).

Self-aligned metal gate with poly silicide for vertical transport field-effect transistors

One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Gate-all-around field effect transistor having multiple threshold voltages

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