International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Globalfoundries U.S. Inc.

Globalfoundries Singapore Pte. Ltd.

Other

Intermolecular, Inc.

Globalfoundaries Inc.

Globalfoundires Inc.

Ruilong Xie

Kangguo Cheng

Chanro Park

Julien Frougier

Xiuyu Cai

Tenko Yamashita

Alexander Reznicek

Min Gyu Sung

Chun-chen Yeh

Juntao Li

Hui Zang

Qing Liu

Andrew Mark Greene

Junli Wang

Balasubramanian Pranatharthiharan

Lars W Liebmann

Daniel Chanemougame

Ali Khakifirooz

Heng Wu

Hoon Sik Kim

Nicolas J Loubet

Veeraraghavan S Basker

Chen Zhang

Su Chen Fan

Jingyun Zhang

Brent A Anderson

Carl John Radens

Laertis Economikos

Steven J Bentley

Xunyuan Zhang

Chih-Chao Yang

Xin Miao

Kisik Choi

Takashi Ando

Dechao Guo

Shom Ponoth

Hemanth Jagannathan

Lawrence Alfred Clevenger

Ajey Poovannummoottil Jacob

Haiting Wang

Pouya Hashemi

Bruce Bennett Doris

David V Horak

Chi-Chun Liu

Oleg Gluschenkov

Bahman Hekmatshoartabari

Guillaume Bouche

Nicholas Anthony Lanzillo

Reinaldo Ariel Vega

Zuoguang Liu

Hiroaki Niimi

Shogo Mochizuki

Fee Li Lie

Ekmini Anuja De Silva

Huiming Bu

Edward J Nowak

Choonghyun Lee

John H Zhang

Wenyu Xu

Ravikumar Ramachandran

Peng Xu

Theodorus E Standaert

Ruqiang Bao

Hosadurga K Shobha

John Ryan Sporre

Mukta G Farooq

Michael Rizzolo

Takeshi Nogami

Garo Jacques Derderian

Injo Ok

Robert Russell Robison

Oscar Van Der Straten

Sanjay C Mehta

Roy Rongqing Yu

Koichi Motoyama

Siva P Adusumilli

Effendi Leobandung

Soon-Cheon Seo

Praneet Adusumilli

Marc Adam Bergendahl

Tao Li

Rajiv V Joshi

Charles W Koburger, Iii

Terence B Hook

Zhenxing Bi

Cheng-Wei Cheng

Kevin Shawn Petrarca

Min-Hwa Chi

Thomas N Adam

Hong Yu

Jinping Liu

Anthony K Stamper

Daniel C Edelstein

Karthik Balakrishnan

Tak H Ning

Son Van Nguyen

Judson Robert Holt

Baozhen Li

Hong He

Jeng-Bang Yau

A structure including a plurality of nanosheet transistors each comprising a gate. A gate protrusion extends from the gate towards the backside of one of the plurality of electronic devices. A first dielectric liner is located flush against the sidewalls of the gate protrusion. A contact via connected to a backside surface of the gate protrusion. A second dielectric liner located flush again the sidewalls of the contact via.

Backside gate via structure using self-aligned scheme

A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source/drain.

Epi growth uniformity with source/drain placeholder

A semiconductor includes a first GAA FET and second GAA FET. The second GAA FET includes a first gate dielectric and second gate dielectric within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.

Heterogeneous gate all around dielectric thickness

A device structure for a phase-change memory device is disclosed. The device structure includes a top electrode, a phase-change material that is recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewall of the top electrode, the sidewall of the phase-change material, and a portion of a top surface and a bottom surface of each of the two layers of the resistive liner material. The device structure includes a heater contacting a bottom electrode and the bottom layer of the resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is under the top electrode.

Phase-change memory device with conductive cladding

An approach for forming semiconductor structure composed of one or more stacked semiconductor devices with a first semiconductor device on a substrate, a first interconnect wiring structure over the first semiconductor device, a second interconnect wiring structure under a second semiconductor device joined to the first interconnect wiring structure, and a third interconnect wiring structure on the second semiconductor device where the first semiconductor device and the second semiconductor device are each one of a memory device or a logic device. The approach includes each of the first interconnect wiring structure, the second interconnect wiring structure, and the third interconnect wiring structure with a contact pitch to the first semiconductor device and to both sides of the second semiconductor device that is less than one hundred nanometers.

Stacked semiconductor devices with topside and backside interconnect wiring

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

Asymmetric gate extension in stacked FET

A semiconductor device includes a first buried power rail (BPR) disposed through etch stop layers and a second BPR disposed in direct contact with the first BPR, where the first BPR has a larger critical dimension (CD) than the second BPR. A bottom surface of the first BPR directly contacts a via-to buried power rail (VBPR) contact. Source/drain contacts (CA) are disposed adjacent the VBPR contact and source/drain regions collectively defining middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed adjacent to the MOL components, and the MOL and BEOL components bond to a carrier wafer. The second BPR is then constructed on the carrier wafer.

Buried power rail at tight cell-to-cell space

A magnetoresistive random access memory (MRAM) device having chip identification using normal operating voltages is provided. No dedicated programming is needed. Instead, programming of the MRAM device is free and random and is a result of providing a magnetic via structure sufficiently close to the magnetic free layer of the magnetic junction tunnel (MTJ) structure such that the magnetic via structure projects a magnetic field that interacts with the magnetic free layer and aligns the magnetization of the magnetic free layer with the magnetization of the magnetic via structure. Thus, the orientation of the magnetization of both the magnetic via structure and the magnetic free layer are aligned in a same direction. The magnetization of the magnetic via structure can thus be used as a physical unclonable function and the MTJ structure can be used to read out this information.

MRAM-based chip identification with free random programming

A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.

Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor

A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.

MRAM integration with self-aligned direct back side contact

Embodiments herein describe semiconductor devices with single diffusion breaks that are narrower than the gates of transistors in those devices. That is, rather than forming the diffusion breaks using a dummy gate (which would result in the diffusion breaks having the same width as the gates of the transistors) the embodiments herein use different means to establish the width of the diffusion break. As a result, the diffusion break can be narrower than traditional diffusion breaks formed using dummy gates, thereby saving area in the semiconductor device.

Narrowing single diffusion break

An integrated circuit (IC) is provided. The IC includes a substrate that includes first and second channels. A shared source or drain (S/D) region is between the first and second channels. The shared source or drain region includes an uppermost surface and further includes a second surface recessed from the uppermost surface and sidewalls extending from the uppermost surface to the second surface to define a recess. First and second gate structures including gate metal are disposed on the first and second channels. An S/D wrap-around contact (WAC) includes a first portion which extends into the recess to contact the second surface and the sidewalls and is wrapped around the S/D region at an exterior of the recess.

Non-self-aligned wrap-around contact in a tight gate pitched transistor

A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

Semiconductor backside contact structure with increased contact area

A semiconductor device includes: a vertical transport field-effect transistor (VTFET) device including a bottom source/drain (S/D) epitaxial layer, a vertical fin channel formed on the bottom S/D epitaxial layer, and a top S/D epitaxial layer formed on the vertical fin channel. The bottom S/D epitaxial layer has an asymmetric profile in cross-section where a first side of the vertical fin channel is aligned with a first side of the bottom S/D epitaxial layer, and the bottom S/D epitaxial layer has a stepped profile that extends beyond a second edge of the vertical fin channel.

VTFET with controlled fin height

A semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region, a metal gate disposed around the vertical semiconductor channel region, where a first portion of the metal gate extends above the vertical semiconductor channel region, and a gate contact entirely above the vertical semiconductor channel region.

Vertical transistor with reduced cell height

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Niskayuna, NY, United States of America

Ruilong Xie