International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Globalfoundries U.S. Inc.

Globalfoundries Singapore Pte. Ltd.

Other

Intermolecular, Inc.

Globalfoundaries Inc.

Globalfoundires Inc.

Ruilong Xie

Kangguo Cheng

Chanro Park

Julien Frougier

Xiuyu Cai

Tenko Yamashita

Alexander Reznicek

Min Gyu Sung

Chun-chen Yeh

Juntao Li

Hui Zang

Qing Liu

Andrew Mark Greene

Junli Wang

Balasubramanian Pranatharthiharan

Lars W Liebmann

Daniel Chanemougame

Ali Khakifirooz

Heng Wu

Hoon Sik Kim

Nicolas J Loubet

Veeraraghavan S Basker

Chen Zhang

Su Chen Fan

Jingyun Zhang

Brent A Anderson

Carl John Radens

Laertis Economikos

Steven J Bentley

Xunyuan Zhang

Chih-Chao Yang

Xin Miao

Kisik Choi

Dechao Guo

Takashi Ando

Shom Ponoth

Hemanth Jagannathan

Lawrence Alfred Clevenger

Ajey Poovannummoottil Jacob

Haiting Wang

Pouya Hashemi

Bruce Bennett Doris

David V Horak

Chi-Chun Liu

Bahman Hekmatshoartabari

Oleg Gluschenkov

Nicholas Anthony Lanzillo

Guillaume Bouche

Reinaldo Ariel Vega

Zuoguang Liu

Hiroaki Niimi

Shogo Mochizuki

Fee Li Lie

Ekmini Anuja De Silva

Huiming Bu

Edward J Nowak

Choonghyun Lee

John H Zhang

Wenyu Xu

Ravikumar Ramachandran

Peng Xu

Theodorus E Standaert

Ruqiang Bao

Koichi Motoyama

Hosadurga K Shobha

John Ryan Sporre

Mukta G Farooq

Michael Rizzolo

Takeshi Nogami

Garo Jacques Derderian

Injo Ok

Robert Russell Robison

Oscar Van Der Straten

Sanjay C Mehta

Roy Rongqing Yu

Siva P Adusumilli

Effendi Leobandung

Soon-Cheon Seo

Praneet Adusumilli

Marc Adam Bergendahl

Tao Li

Rajiv V Joshi

Charles W Koburger, Iii

Terence B Hook

Zhenxing Bi

Cheng-Wei Cheng

Min-Hwa Chi

Kevin Shawn Petrarca

Thomas N Adam

Hong Yu

Jinping Liu

Anthony K Stamper

Daniel C Edelstein

Karthik Balakrishnan

Tak H Ning

Son Van Nguyen

Judson Robert Holt

Baozhen Li

Hong He

Jeng-Bang Yau

A gate-all-around field effect transistor device is provided. The gate-all-around field effect transistor device includes one or more channel layers on a substrate. The gate-all-around field effect transistor device further includes an inner spacer wrapped around four sides of an end portion of each of the one or more channel layers. The gate-all-around field effect transistor device further includes a portion of an inner spacer liner between a portion of an upper most channel layer and a portion of an outer spacer.

Gate-all-around field-effect-transistor with wrap-around-channel inner spacer

An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a source drain contact above and contacting a source drain region of a semiconductor device. The interconnect structure also includes a via above and contacting the source drain contact. The via includes a lower portion with an uppermost surface that contacts a lowermost surface of an interlayer dielectric.

Liner-less via contact

A microelectronic structure including a first stacked FET device that includes a first bottom FET device and a first upper FET device. The first bottom FET device include a plurality of first bottom channel layers, and the first upper FET device includes a plurality of first upper channel layers. A bottom gate that surrounds the plurality of first bottom channel layers and an upper gate that surrounds the plurality of first upper channel layers. A gate protrusion that extends downwards from the backside of the upper gate to connected to the bottom gate. The gate protrusion partially overlaps with a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps with an upper gate cut region of the first upper stacked FET device.

Stacked FET with extremely small cell height

A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.

Backside power rail with tight space

A hybrid stacked semiconductor device includes a nanosheet stack on a substrate and an all-around gate. The nanosheet stack includes a first stack portion and a second stack portion. The first stack portion includes first channels. The second stack portion is stacked on the first stack portion, and includes second channels. The all-around gate includes a first gate portion that wraps around the first channels and a second gate portion that wraps around the second channels. A first gate extension contacts the first gate portion and the second gate extension contacts the second gate portion. At least one gate contact contacts the first gate extension to establish conductivity with the first gate portion and contacts the second gate extension to establish conductivity with the second gate portion.

Hybrid stacked field effect transistors

A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Gate induced drain leakage reduction in FinFETs

A microelectronic structure comprises a first interconnect line at a first interconnect level, a second interconnect line at a second interconnect level, and at least one via connecting the first interconnect line at the first interconnect level to the second interconnect line at the second interconnect level. The at least one via comprises a vertical section and at least one horizontal section, the at least one horizontal section being in contact with at least a portion of one of a top surface of the first interconnect line and a bottom surface of the second interconnect line.

Interconnect structures with vias having vertical and horizontal sections

A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material, a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate, the metal link disposed above the second dielectric material, a first source/drain (S/D) contact disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

Semiconductor device having hybrid middle of line contacts

A semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. The second metallization layer includes a second plurality of metal containing lines. A first group of the second plurality of metal containing lines is disposed within the first metallization layer. The first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.

Semiconductor structure with backside metallization layers

A structure is provided that includes a first metal level including a first metal line, a second metal level spaced apart from the first metal level and including a second metal line, and a first metal via structure connecting the first metal line to the second metal line. The first metal via structure directly contacts a sidewall surface and a horizontal surface of the first metal line.

Wrap around metal via structure

The embodiments herein describe a crossbar VFET where the crossbar channel (or fin) that extends between a pair of channels (fins) has reduced corner rounding, or no corner rounding. This can be achieved by developing a masking feature before etching the channels in the VFET that results in reduced, or no corner rounding in the channel structure etched using the masking feature.

Cross bar vertical FETs

Embodiments are disclosed for a method for fabricating a semiconductor device. The method includes forming a recess under a region for a source/drain (S/D). The method further includes depositing a sacrificial placeholder liner conformally. Additionally, the method includes performing a sacrificial material overfill. Further, the method includes performing an etch back of the sacrificial material overfill. Also, the method includes performing S/D epitaxial (epi) growth over a remaining placeholder sacrificial liner to generate an S/D epi for the S/D.

Semiconductor device with void under source/drain region for backside contact

A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

Vertical transport field effect transistor (VTFET) with backside wraparound contact

A structure including a plurality of nanosheet transistors each comprising a gate. A gate protrusion extends from the gate towards the backside of one of the plurality of electronic devices. A first dielectric liner is located flush against the sidewalls of the gate protrusion. A contact via connected to a backside surface of the gate protrusion. A second dielectric liner located flush again the sidewalls of the contact via.

Backside gate via structure using self-aligned scheme

A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source/drain.

Epi growth uniformity with source/drain placeholder

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Ruilong Xie