Other

Az Power, Inc

University of California

Ruigang Li

Zheng Zuo

Da Teng

Na Ren

Xiaotian Yu

Bochao Huang

Dengtao Zhao

Bei Li

Jianlin Liu

Yan Zhu

A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Merged PiN Schottky (MPS) diode with plasma spreading layer and manufacturing method thereof

In one aspect, a semiconductor device may include a semiconductor substrate formed of silicon carbide; and an edge termination having a first metal layer and a second metal layer, wherein the first metal layer is deposited and patterned spacedly on the semiconductor substrate and the second metal layer is deposited and patterned onto at least a portion of the spaced first metal layer and onto the semiconductor substrate between said spaced first metal layer, and wherein the first metal layer comprises a high work function metal, while the second metal layer comprises a low work function metal. In one embodiment, the high work function metal includes Silver, Aluminum, Chromium, Nickel, and Gold; and the low work function metal includes Titanium and Nickel Silicide.

Metal terminal edge for semiconductor structure and method of forming the same

A method for manufacturing a SiC mixed trench Schottky diode may include steps of providing a substrate and an epitaxial layer on top of the substrate; forming a plurality of trenches on a surface of the epitaxial layer; conducting ion implantation at a bottom portion of each trench; conducting ion implantation at sidewalls of each trench; forming an ohmic contact metal at a bottom portion of the Schottky diode; forming a Schottky contact metal on top of the epitaxial layer and in the trenches. In one embodiment, the substrate is an Ntype SiC and the epitaxial layer is an Ntype SiC. In another embodiment, the step of forming a plurality of trenches on a surface of the epitaxial layer may include the step of etching the surface of the epitaxial layer by either dry etching or wet etching.

Mixed trench junction barrier Schottky diode and method fabricating same

In one aspect, a method for manufacturing a Schottky diode with double P-type epitaxial layers may include steps of: providing a substrate; forming a first epitaxial layer on top of the substrate; forming a second epitaxial layer on top of the first epitaxial layer; depositing a third epitaxial layer on top of the second epitaxial layer; patterning the second and third epitaxial layers to form a plurality of trenches in the second and third epitaxial layers; depositing a first ohmic contact metal on a backside of the substrate; forming a second ohmic contact metal on top of the patterned third epitaxial layer; forming a Schottky contact metal at a bottom portion of each trench; and forming a pad electrode on top of the Schottky contact metal. In one embodiment, the second and third epitaxial layers can be made by Ptype SiC and Ptype SiC, respectively.

Schottky diode having double p-type epitaxial layers with high breakdown voltage and surge current capability

A passivation method for a silicon carbide (SiC) surface may include steps of providing a silicon carbide surface, depositing a thin metal layer on the silicon carbide surface, forming a first passivation layer on the metal layer at low temperature, and generating a dielectric layer by a reaction between a gas/liquid ambient and the thin metal layer. In one embodiment, the thin metal layer is deposited on the silicon carbide surface by sputtering, e-beam evaporation, electroplating, etc. In another embodiment, the metal may include, but not limited to, aluminum, magnesium, etc. In a further embodiment, the passivation layer can be a low temperature oxide and/or nitride layer. In still a further embodiment, the dielectric layer can be aluminum oxide, titanium di-oxide etc. The passivation method for a silicon carbide (SiC) may further include a step of forming a second passivation layer on the first passivation layer.

Passivation for silicon carbide (SiC) device and method for fabricating same

A method for fabricating a silicon carbide power device may include steps of: forming a first n-type silicon carbide layer on top of a second n-type silicon carbide layer; depositing a first metal layer on the first silicon carbide layer; patterning the first metal layer; depositing and patterning a dielectric layer onto at least a portion of the pattered first metal layer; and depositing and patterning a second metal layer to form a Schottky barrier. In one embodiment, the first metal layer is a high work function metal layer, which may include Silver, Aluminum, Chromium, Nickel and Gold. In another embodiment, the second metal layer is called a 'Schottky metal' layer, which may include Platinum, Titanium and Nickel Silicide.

Schottky barrier structure for silicon carbide (SiC) power devices

In one embodiment, a memory device includes a substrate, a tunneling oxide, a silicide nanocrystal floating gate, and a control oxide. The tunneling oxide is positioned upon a first surface of the substrate, the silicide nanocrystal floating gate is positioned upon the tunneling oxide, and the control oxide positioned upon the nanocrystal floating gate.

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Los Angeles, CA, United States of America

Ruigang Li