Xilinx, Inc.

Ruibing Lu

Sabyasachi Das

Zhiyong Wang

Aaron Ng

Aman Gayasen

Rajat Aggarwal

Sreesan Venkatakrishnan

Niyati Shah

Lin Chai

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing post-routing and post-placement physical synthesis optimizations. One of the methods includes receiving a circuit design of a multi-die integrated circuit (IC) device having a first die connected with a second die, wherein the circuit design specifies a respective initial component placement of each of a plurality of components on the first die and the second die. A first driver on the first die having a plurality of loads on the second die is selected. A transmit site is selected on the first die that reduces a distance between the first driver and a load of the plurality of loads on the second die. The circuit design is modified including moving the first driver to the selected transmit site on the first die.

Post-placement and post-routing physical synthesis for multi-die integrated circuits

Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.

Timing optimization of memory blocks in a programmable IC

Disclosed approaches for processing a circuit design include determining first slacks of cells, including a target cell, coupled to receive a clock signal through a first clock leaf. The first slacks are based on a current delay value specified for a first programmable delay circuit. The method predicts second slacks of the cells based on another delay value specified for the first programmable delay circuit, and then determines whether or not the second slacks indicate a degradation in timing relative to the first slacks. The current delay value of the first programmable delay circuit is adjusted to the other delay value in response to determining the second slacks indicates no degradation in timing. The target cell is reconnected to receive the clock signal from a second clock leaf having a second programmable delay circuit specified with the other delay value in response to determining the second slacks indicates degradation in timing.

Targeted delay optimization through programmable clock delays

A method of circuit design may include synthesizing a circuit design using a processor and, for the synthesized circuit design, selectively reducing, using the processor, fanout of nets having a number of loads exceeding a first threshold number of loads and having a selected netlist connectivity. The method may include placing the circuit design using a processor and, for the placed circuit design, selectively reducing, using the processor, fanout of nets according to at least one of a number of loads or criticality.

Fanout optimization to facilitate timing improvement in circuit designs

A method of circuit design may include identifying, using a processor, a timing critical path within a first look-up table structure in a circuit design and restructuring, using the processor, the first look-up table structure into a functionally equivalent second look-up table structure. The second look-up table structure may include fewer look-up tables serially coupled in the timing critical path than the first look-up table structure. The method may include placing, using the processor, the second look-up table structure and routing, using the processor, the second look-up table structure.

Look-up table restructuring for timing closure in circuit designs

Post-routing processing of a circuit design may include determining, using a processor, a baseline delay for a path of a routed circuit design, comparing, using the processor, the baseline delay of the path with a timing constraint of the path, and selectively applying, according to the comparing, a structural netlist optimization to the path resulting in an optimized path using a processor.

Post-routing structural netlist optimization for circuit designs

A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

Interactive multi-step physical synthesis

In an example, a method of implementing a circuit design for an integrated circuit (IC) includes: placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths, and executing a timing analysis to determine a timing profile of the physical description. The method further includes optimizing the physical description by performing a plurality of iterations of: comparing the timing profile with a timing constraint to select a candidate set of paths having negative slack from the plurality of paths in the physical description; and modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack. The method further includes generating a physical implementation of the circuit design for the IC based on the physical description.

Opportunistic candidate path selection during physical optimization of a circuit design for an IC

In an approach for processing a circuit design by a programmed processor, a placed circuit design that has been placed on programmable resources of a programmable integrated circuit (IC) is input. A critical path is determined from a first sequential element to a second sequential element assigned to the placed circuit design. A first clock buffer that provides a clock signal to the first and second sequential elements is determined, and an unused clock buffer is selected based on proximity to the first sequential element. The circuit design is modified to include the unused clock buffer as a second clock buffer coupled to receive a clock signal in parallel with the first clock buffer and to provide a clock signal to the first sequential element.

Selective addition of clock buffers to a circuit design

Physical optimization for timing closure for an integrated circuit includes processing a circuit design at least partially through a design flow to a late stage of the design flow. Using a processor, a baseline delay is calculated for each of a plurality of paths of the circuit design. A slack for each of the plurality of paths is determined. Physical optimization further includes selecting a path of the circuit design that meets a selection criterion according, at least in part, to the slack of the path, applying, using the processor, a physical optimization to the selected path resulting in an optimized path, and calculating a delay of the optimized path. The optimized path is incorporated into the circuit design only responsive to determining that the delay of the optimized path is less than the baseline delay of the selected path.

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Santa Clara, CA, United States of America

Ruibing Lu