Taiwan Semiconductor Manufacturing Comp. Ltd.

Ruey-Yun Shiue

Yuan-Lung Liu

Chung Chang Liu

Chin-Kai Liu

Pi-Chen Shieh

Jiue Wen Weng

Wen-Teng Wu

Jing-Cheng Lin

Wen-Chun Huang

Fu-Jier Fan

Hsi-Kuei Cheng

Kuo-Chio Liu

Chih-Hsien Lin

Yi-Hsun Wu

Lin-June Wu

Hsiang-Tai Lu

Ho-Yin Yiu

Chien-Chen Li

Chin-Shan Hou

Chu-Wei Hu

Yu-Jui Wu

Ming-Hsien Chen

Huang-Sheng Lin

Sung-Mu Hsu

Tzi-Yi Shieh

Aaron Wang

Jine-Wen Weng

Hsiang-Wei Wang

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.

Two step molding grinding for packaging applications

A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processes semiconductor wafer is provided having all metal levels completed. A blanket dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patters, after which a passivation layer is formed.

Bonding pad structure to minimize IMD cracking

Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.

Top via pattern for bond pad structure

A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processed semiconductor wafer is provided having all metal levels completed. A blank dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patterns, after which a passivation layer is formed.

Mesh pad structure to eliminate IMD crack on pad

A new method of forming selective salicide is described, whereby low resistance salicide is formed on exposed MOSFET CMOS, narrow polysilicon gates and lightly doped source/drains (LLD) without affecting device electrical performance. This invention describes a selective salicide process forming titanium salicide on exposed MOSFET CMOS devices using ion implantation for effective ion mixing between a two-step titanium deposition process. First, a thin layer of titanium is deposited on exposed polysilicon gate and exposed lightly doped source/drain (LLD) regions. Second, a low energy ion implantation of Si&plus; is performed with peak dose targeted to be just below the Ti/Si interface. Third, an initial rapid thermal anneal (RTA) is performed followed by a selective etch to remove unwanted, excess titanium. The final step is another rapid thermal anneal (RTA) to fully convert the silicide from C49 crystal structure to the preferred C54 structure, for low resistivity. Hence, low resistivity self-aligned silicide is formed on narrow polygates and lightly doped source/drains (LLD) without affecting device electrical performance.

Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology

A method for making metal capacitors for deep submicrometer processes for integrated circuits is described. The method provides metal capacitors with high capacitance per unit area, low voltage coefficients, and excellent capacitance distribution (uniformity) across the substrate. The method involves depositing a first insulating layer on a substrate having completed semiconductor devices. A first metal layer is deposited and patterned to form bottom electrodes and interconnecting metal lines. A thin capacitor dielectric layer is deposited, and a thin second metal or TiN layer is deposited and patterned to form the top electrodes. A thick second insulating layer is deposited and planarized, and an array of via holes are etched to the top electrodes to provide for low-resistance contacts and via holes for the interconnecting metal lines. A third conducting metal layer is deposited over the second insulating layer and in the via holes, and is patterned to form a thick metal plate over the capacitors to provide low-resistance contacts to the capacitors and concurrently to form the next level of metal interconnections.

Method for making metal capacitors for deep submicrometer processes for

A method is disclosed for improving the ESD protection of gate oxide in ultra large scale integrated circuits of 0.35 .mu.m technology or less, approaching 0.25 .mu.m. This is accomplished by providing a silicon substrate and forming thereon product FET device circuits and ESD protection device circuits. In forming the ESD source/drain regions, the implantation species is changed from phosphorous to boron, thereby reducing junction breakdown voltage. Ion implantation is performed judiciously in areas with high leakage and capacitance. Hence improvement is accomplished though reduced breakdown voltage, as well as through reduced leakage and capacitance of the junction. Furthermore, ion implantation is performed using a photoresist mask prior to the formation of silicidation over the contact area. This avoids the problem of silicide degradation and the concomitant increase in contact resistance through the transportation of metal ions into depletion region of junction during high energy ESD implantation.

ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide process

A bond pad structure and method of forming the bond pad structure which provides for reliable interconnections between the bond pad structure and the next level of circuit integration. The bond pad structure uses three metal pads separated by layers of dielectric. Via plugs are formed between the first and second metal pads and between the second and third metal pads. The via plugs are formed in a diamond shape with respect to the metal pads. The metal pads are squares with the same orientation. The periphery of the via plugs forms a square rotated 45.degree. with respect to the square metal pads.

Bond pad structure for the via plug process

A test structure is described which indicates the occurrence of plasma damage resulting from back-end-of-line processing of integrated circuits. The structure consists of a MOSFET which is surrounded by a conductive shield grounded to the substrate silicon along its base perimeter. The walls of the shield are formed from the sundry levels of conductive layers applied during the integrated circuit interconnection metallization beginning with contact metallurgy which is connected to a diffusion within the substrate. This diffusion is formed within a trench in field oxide surrounding the MOSFET and is of the same conductive type as the substrate material. The top conductive plate of the test structure is formed from a selected metallization layer of the integrated circuit. By forming test structures with top conductive plates formed from two different metallization levels, the plasma damage incurred during the intervening processing steps can be uniquely determined. The test structures may be formed within the wafer saw-kerf area or within wafer test sites. Testing is accomplished by measuring shifts in threshold voltage and drive current before and after gate current stressing. Differences in these shifts from one metallization level to another indicate damage in the MOSFETs gate region has occurred during the processing steps which lie between the depositions of the top conductive plates of the two shields.

Plasma damage monitor

Method of forming bond pad structure for the via plug process

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Hsin-Chu, Taiwan

Ruey-Yun Shiue