Peking University

Hangzhou Weiming Xinke Technology Co.. Ltd

Cadence Design Systems, Inc.

Ru Huang

Jiewen Fan

Yangyuan Wang

Qianqian Huang

Runsheng Wang

Xia An

Xing Zhang

Yimao Cai

Li Wang

Yujie Ai

Xin Huang

Zhan Zhan

Quanxin Yun

Jibin Zou

Yinglong Huang

Shuai Sun

Xiaoyan Xu

Min Li

Yingxin Qiu

Jia Qi Li

Zhiqiang Li

Yue Pan

Dong Yan Yang

Poren Tang

Yu Jia Tang

Fei Tan

Le Ye

Gengyu Yang

Meng Lin

Zhihua Hao

Yujie Al

Shuangshuang Pu

Muxi Yu

Shiqiang Qin

Yuancheng Yang

Shenghu Tan

Changze Liu

Hao Zhang

Lijie Zhang

Yue Guo

Jiaxin Wang

Chunlei Wu

Jing Zhuge

Pengqiang Liu

Wenliang Bai

Yichen Fang

Haoran Xuan

Qiang Li

Chao Wang

Jun Mao

Gong Chen

Hanming Wu

Yanhui Li

Weihai Bu

Hui Feng

Alvin Chen

Zongwei Wang

Jushan Xie

Kaifeng Wang

Song Mei

Zhenxing Zhang

Jiayi Wang

Zhiyuan Fu

Shoubin Xue

Zhexuan Ren

Gensong Li

Chunhui Fan

Ming Li

Tianyi Liu

Weikang Wu

Jin Luo

Guangjun Yu

Han Xiao

Liangxi Huang

Zhixuan Wang

Si-Yu Liao

Yefan Liu

Chunyi Huang

Tianlei Guo

Shaofeng Guo

Shihui Yin

Zhuoqing Yu

Huailin Liao

Zhenni Wan

Disclosed in the present application are a logic circuit design method and apparatus, and a storage medium. The method comprises: designing and generating an initial MOSFET-TFET hybrid logic circuit, the MOSFET-TFET hybrid logic circuit comprising several logic gates; in the series branch of the initial MOSFET-TFET hybrid logic circuit, replacing a first type of TFET with a MOSFET; the first type of TFET being directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates. The logic circuit design method of the present application overcomes the defect of excessive current attenuation caused by the TFET in the series branch by replacing the first type of TFET in the series branch of the initial logic circuit with a MOSFET. The first type of TFET is a TFET that is directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates.

Logic circuit design method

Disclosed is an embedded semiconductor random access memory structure, including a hafnium oxide-based ferroelectric storage element suitable for storing information, and a tunneling field effect transistor connected to the storage element. The tunneling field effect transistor is suitable for controlling the hafnium oxide-based ferroelectric storage element to perform read and write operations. A semiconductor memory array can be formed by repeating the above memory structures. A control method for the memory structure includes steps of writing 0, writing 1, reading, and writing back.

Embedded semiconductor random access memory structure and control method therefor

A CMOS-MEMS humidity sensor includes a complementary metal oxide semiconductor (CMOS) ASIC readout circuit and a microelectromechanical system (MEMS) humidity sensor. The MEMS humidity sensor is provided on the ASIC readout circuit. The ASIC readout circuit includes a substrate, a heating resistor layer located above the substrate, a metal layer located above the heating resistor layer, and dielectric layers. The substrate, the heating resistor layer, and the metal layer are partitioned by dielectric layers. The MEMS humidity sensor includes an aluminum electrode layer, a passivation layer located above the aluminum electrode layer, and a humidity sensitive layer located above the passivation layer. The provision of heating resistors in the ASIC circuit realizes the heating function and satisfies the requirements of the standard CMOS process, so that the CMOS-MEMS integrated humidity sensor can be used stably under low temperature and high humidity conditions.

CMOS-MEMS humidity sensor

Disclosed is a method for implementing an adaptive stochastic spiking neuron based on a ferroelectric field effect transistor, relating to the technical field of spiking neurons in neuromorphic computing. Hardware in the method includes a ferroelectric field effect transistor (fefet), an n-type mosfet, and an l-fefet formed by enhancing a polarization degradation characteristic of a ferroelectric material for the ferroelectric field-effect transistor, wherein a series structure of the fefet and the n-type mosfet adaptively modulates a voltage pulse signal transmitted from a synapse. The l-fefet has a gate terminal connected to a source terminal of the fefet to receive the modulated pulse signal, and simulates integration, leakage, and stochastic spike firing characteristics of a biological neuron, thereby implementing an advanced function of adaptive stochastic spike firing of the neuron.

Method for implementing adaptive stochastic spiking neuron based on ferroelectric field effect transistor

A method for characterizing a fluctuation induced by single particle irradiation in a device. A plurality of devices varying in size are tested respectively before and after irradiation to obtain threshold voltage distribution, such that a threshold voltage fluctuation induced by irradiation is obtained and used to correct a process fluctuation model, so as to correct a design margin of the devices working under the irradiation.

Method for characterizing fluctuation induced by single particle irradiation in a device and application thereof

A method, a system and a non-transitory machine-readable storage medium are provided. In one or more aspects, a computer-implemented method for bias temperature instability (BTI) calculation of a device includes simulating the device, using an electronic design automation tool. The simulation includes determining a first degradation value after applying a first sequence of stress values to the device for a first plurality of time steps. The simulation further includes determining a first degradation recovery value after the first plurality of time steps. The simulation further includes determining a first recovered degradation value after the first plurality of time steps by combining the first degradation value and the first degradation recovery value. The first degradation value, the first degradation recovery value, and the first recovered degradation value are associated with one or more model parameters of the device. The simulation is a transient analysis simulation, and the device is a FINFET or MOSFET device.

Method of bias temperature instability calculation and prediction for MOSFET and FinFET

Disclosed is a resistive random access memory, comprising a substrate, an insulating layer, a bottom electrode, a resistive material film, and a top electrode in an order from bottom to top, wherein the resistive material film is a four-layer structure composed of a same metal oxide; and the four layers in the four-layer structure from bottom to top have resistance values which are increased one after another by more than 10 times, oxygen concentrations which are increased one after another and thickness which are decreased one after another. The present invention may achieve complete formation-rupture of oxygen vacancy conductive filaments (CF) in each layer by dividing the resistive material film of the same metal oxide into four layers according to the different oxygen concentrations, so as to control accurately the resistance values, so that 2-bit storage with high uniformity is achieved.

Resistive random access memory with high uniformity and low power consumption and method for fabricating the same

The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers. The interlayer has a doping type which is opposite to that of the substrate so that a shunt PN junction is formed between the interlayer and the substrate, and the shunt PN junction has an electrode not connected to the drain so that a part of the charges collected by the shunt PN junction are not output to the drain and are ultimately guided out of the multi-gate devices, thereby weakening the influence of the single-event effect. In comparison with a multi-gate device of prior art, the multi-gate device of the present invention may effectively suppress the sensitivity of the device to single event irradiation in the event that the layout areas of the two types of devices are almost same.

Radiation-hardened-by-design (RHBD) multi-gate device

The present invention discloses a short-gate tunneling field effect transistor having a non-uniformly doped vertical channel and a fabrication method thereof. The short-gate tunneling field effect transistor has a vertical channel and the channel region is doped in such a slowly-varied and non-uniform manner that a doping concentration in the channel region appears as a Gaussian distribution along a vertical direction and the doping concentration in the channel near the drain region is higher while the doping concentration in the channel near the source region is lower; and double control gates are formed at both sides of the vertical channel and the control gates form an L-shaped short-gate structure, so that a gate underlapped region is formed in the channel near the drain region, and a gate overlapped region is formed at the source region.

Short-gate tunneling field effect transistor having non-uniformly doped vertical channel and fabrication method thereof

The present invention discloses a method for integrating a vertical nanowire transistor and belongs to a field of field effect transistor logic device in a CMOS ultra-large scale integrated circuit (ULSI). The method realizes the integration of the vertical-nanowire transistor by combining selective epitaxy and replacement gate on sidewall. In comparison with an existing method for forming a vertical nanowire channel by etching, a size and shape of a cross section of a device channel can be accurately controlled, a consistency of device characteristic can be improved, and an etching damage during the forming of a channel in the existing method can be avoided, thereby the device performance can be improved.

Integration method for a vertical nanowire transistor

The present invention discloses a tunneling field effect transistor having a three-side source and a fabrication method thereof, referring to field effect transistor logic devices and circuits in CMOS ultra large scale integrated circuits (ULSI). By means of the strong depletion effect of the three-side source, the transistor can equivalently achieve a steep doping concentration gradient for the source junction, significantly optimizing the sub-threshold slope of the TFET. Meanwhile, the turn-on current of the transistor is boosted. Furthermore, due to a region uncovered by the gate between the gate and the drain, the bipolar conduction effect of the transistor is effectively inhibited, and on the other hand, in the small-size transistor a parasitic tunneling current at the corner of the source junction is inhibited. The fabrication method is simple and can be accurately controlled. By forming the channel region using an epitaxy method subsequent to etching, it facilitates to form a steeper doping concentration gradient for the source region or form a hetero-junction. Moreover, the fabrication flow of the post-gate process facilitates to integrate a high-k gate dielectric/a metal gate having good quality, further improving the performance of the transistor.

Tunneling field effect transistor having a three-side source and fabrication method thereof

The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeOon the surface, and further depositing a layer of metal. The stability Ce&#x2014;O&#x2014;Ge bonds can be formed at the interface after rare earth oxides CeOare in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeObetween the metal and the germanium substrate is smaller relative to the case of SiN, AlO, GeNor the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeOdielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity.

Preparation method of a germanium-based schottky junction

Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and the drain; forming an oxidation isolation layer; forming a gate structure and a source/drain structure; and forming a metal contact and a metal interconnection. By means of the method herein, it is very easy to fabricate the FinFET with separated double gates on the bulk silicon wafer, and the overall process flow is completely compatible with the conventional silicon-based very large scale integrated circuit manufacturing technology. Thus, the method herein is simple, convenient and has a short process period, greatly economizing the cost of the silicon wafer. In addition, by employing the FinFET with separated double gates fabricated by the method according to the invention, the short channel effect can be effectively suppressed. Further, the power consumption of the device can be further reduced through the special multi-threshold characteristic of the device with separated double gates.

Method for fabricating FinFET with separated double gates on bulk silicon

The present invention discloses an organic resistive random access memory and a preparation method thereof. The memory uses silicon as a substrate, and has a MIM capacitor structure having a vertical memory unit, where the MIM structure has a top electrode of Al, a bottom electrode of ITO, and an middle functional layer of parylene, wherein, a parylene layer as the functional layer is formed by performing deposition multiple times, where the deposition of AlOis performed once by ALD between each two deposition of parylene. A critical region which is in favor of forming a conductive channel could be formed by controlling the deposition area of AlO, and further control the electrical characteristics of the memory. Through the present invention, the cycle-to-cycle and device-to-device uniformity could be effectively improved, without changing the basic structure of the memory.

Organic resistive random access memory and a preparation method thereof

A method for fabricating multiple layers of ultra narrow silicon wires comprises the steps of fabricating wet-etch masking layers of silicon; forming a Fin and source/drain regions located at both ends thereof by epitaxy; forming the multiple layers of ultra narrow silicon wires. The present invention has advantages in that: the atom layer depositing may define the position of the ultra narrow silicon wires accurately, having a good controllability; the anisotropic wet-etch for silicon is performed in a self-stop manner and has a large process window, so that the cross-section shape of the nanowires formed by wet-etch is uniform and smooth. The method to form multiple layers of wet-etch masks at the sidewalls of Fins, in which wet-etch masking layers are formed prior to the epitaxy of Fins is a simple process, so that the multiple sidewall wet-etch masking layers may be obtained by only one etching to the epitaxy window, regardless of the numbers of the wet-etch masking layers; a wire with a diameter less than 10 nm may be fabricated by virtue of the oxidation technology, and thus satisfies the small size devices; the TMAH solution, which is simple and safe to control, is used in the wet-etch for polysilicon, and metal ions are not introduced and thus suitable for the integrated circuit manufacturing process; the method according to the present invention is fully compatible with the planar transistor based on the bulk silicon, and thus the process cost is small.

Method for fabricating multiple layers of ultra narrow silicon wires

Growing community of inventors

Beijing, China

Ru Huang