Northrop Grumman Systems Corporation

Westinghouse Electric Corporation

Rowland C Clarke

Richard R Siergiej

Charles D Brandt

Anant K Agarwal

Michael Edward Aumer

Eric Jonathan Stewart

Saptharishi Sriram

Stephen Van Campen

Graeme W Eldridge

Robert Samuel Howell

Donovan L Barrett

Michael C Driver

Jeffrey David Hartman

Li-shu Chen

Maurice H Hanes

Marc Eisenzweig Sherwin

Silai V Krishnaswamy

Ranbir Singh

Ty Richard McNutt

Darren Thomson

Hudson McDonald Hobgood

Albert A Burk, Jr

Erica C Elvey

Michel E Aumer

Ty R Mcnutt

In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode. A first electrical connection ties the gates of the first VJFET, the gates of the second VJFET, and the anode of the JBS diode to a common gate electrode and a second electrical connection ties the source of the first VJFET and the source of the second VJFET to a common source electrode.

Power switching transistors

A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiOand a third layer of Si, has its third layer of Si bonded to the Si deposited on the SiC wafer, forming a unitary structure. The first layer of Si and the intermediate layer of SiOof the SOI are removed, leaving a pure third layer of Si on which various semiconductor devices may be fabricated. The third layer of Si and deposited Si layer may be removed over a portion of the substrate arrangement such that one or more semiconductor devices may be fabricated on the SiC wafer while other semiconductor devices may be accommodated on the pure third layer of Si.

Method of making a semiconductor structure for high power semiconductor devices

A dual gate power switch comprised of a vertical arrangement of a normally off SIT (static induction transistor) in series with a normally on SIT in a monolithic semiconductor structure. The structure includes a first pillar having at the base thereof laterally extending shoulder portions having sections of a first gate for controlling the normally off SIT. The structure includes a second pillar, of a width greater than the first pillar and which also has laterally extending shoulder portions having sections of a second gate for controlling the normally on SIT. Contacts are provided for SIT operation.

Vertically integrated dual gate transistor structure and method of making same

First and second semiconductor wafers are bonded together, with at least one of the wafers having a first layer of silicon, an intermediate oxide layer and a second layer of silicon. The first silicon layer is initially mechanically reduced by around 80% to 90% of its thickness. The remaining silicon layer is further reduced by a plasma etch which may leave an uneven thickness. With appropriate masking the uneven thickness is made even by a second plasma etch. Remaining silicon is removed by a dry etch with XeF2 or BrF3 to expose the intermediate oxide layer. Prior to bonding, the semiconductor wafers may be provided with various semiconductor devices to which electrical connections are made through conducting vias formed through the exposed intermediate oxide layer.

Method of thinning a semiconductor structure

A solid state light emitting device having a plurality of semiconductor finger members with side walls perpendicular to a substrate. Multiple quantum wells are formed on the side walls, and are also perpendicular to the substrate. Each multiple quantum well is sandwiched between the side wall of a finger member and a second semiconductor member of a conductivity type opposite to that of the finger member. Ohmic contacts are applied to the finger members and second semiconductor member for receiving a voltage. The device is GaN based such that emitted light will be in the UV region.

Semiconductor light source and method of making

A HEMT type device which has pillars with vertical walls perpendicular to a substrate. The pillars are of an insulating semiconductor material such as GaN. Disposed on the side surfaces of the pillars is a barrier layer of a semiconductor material such as AlGaN having a bandgap greater than that of the insulating material of the pillars. Electron flow is confined to a narrow channel at the interface of the two materials. Suitable source, drain and gate contacts are included for HEMT operation.

HEMT device and method of making

A static induction transistor having source, drain and gate regions. Channel regions are defined between adjacent gates and a drift region is defined from the ends of the channel regions to the drain. The channel and drift regions have predetermined doping concentrations with the doping concentration of the channel regions being greater than the doping concentration of the drift region.

Static induction transistor

A silicon carbide metal semiconductor field effect transitor fabricated on silicon carbide substrate with a layer which suppresses surface effects, and method for producing same. The surface-effect-suppressive layer may be formed on exposed portions of the transistor channel and at least a portion of each contact degenerate region. The surface-effect-suppressive layer may be made of undoped silicon carbide or of an insulator, such as silicon dioxide or silicon nitride. If the surface-effect-suppressive layer is made of silicon dioxide, it is preferred that the layer be fabricated of a combination of thermally-grown and chemical vapor deposition deposited silicon dioxide.

Silicon carbide power MESFET with surface effect supressive layer

A static induction transistor having a silicon carbide substrate upon which is deposited a silicon carbide layer arrangement. The layer arrangement has a plurality of spaced gate regions for controlling current flow from a source region to a drain region vertically spaced from the source region by a drift layer. The pitch distance p between gate regions is 1 to 5 microns and the drift layer thickness d is also 1 to 5 microns. In one embodiment the source regions are positioned alternatively with the gate regions and are formed in a top layer of high doping concentration. In another embodiment the gate regions are ion implanted in the layer arrangement. In another embodiment the structure includes a dual oxide layer covering gate and source or drain regions, and in yet another embodiment contacts for the drain, source and gate regions are located on the same side of the substrate member.

Silicon carbide static induction transistor structure

A method of aligning a gate and a source of a silicon carbide static induction transistor comprising the steps of depositing an oxide layer over the transistor, forming oxide spacers from the oxide layer where the oxide spacers are adjacent the source, depositing a metal layer over the transistor and removing the oxide spacers so that the resulting gates are accurately aligned with the source.

Self-aligned gate fabrication process for silicon carbide static

A static induction transistor includes a substrate and a drift layer with different doping levels. At least two mesas are formed on the drift layer and a heavily doped region is positioned on a top surface of each of the mesas. A gate contact extends along a bottom of a recess between the mesas and along a side of each of the mesas forming the recess. The gate contact also extends along a portion of the top surface of each of the mesas. In one embodiment of the invention, a notch is formed in the top surface of the mesas between the gate contact and the heavily doped region.

Static induction transistors

A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed. Furthermore, recessed or planar MOS gates may be utilized, as may a PN junction gate.

Silicon carbide static induction transistor

A method for epitaxially growing a-axis .alpha.-SiC on an a-axis substrate is provided. A section is formed from the SiC crystal by making a pair of parallel cuts in the crystal. Each of these cuts is parallel to the c-axis of the crystal. The resulting section formed from the crystal has opposing a-face surfaces parallel to the c-axis of the crystal. A gas mixture having hydrocarbon and silane is passed over one of the a-face surfaces of the section. The hydrocarbon and silane react on this a-face surface to form an epitaxial layer of SiC. Preferably, the SiC is grown at a temperature of approximately 1450.degree. C.

Method for epitaxially growing .alpha.-silicon carbide on a-axis

A bonded structure is described consisting of a semiconductor wafer, preferably gallium arsenide, soldered to a substrate material. A method for forming the structure is also described. The structure provides mechanical support and thermal conductivity for the wafer, as well as a multitude of connections through the substrate material at predetermined locations on the wafer. The substrate material and the soldering process are selected to minimize the resulting stresses in the wafer. A pattern of pads consisting of a refractory metal covered by a solder material is formed on the substrate to maintain space for excess solder in order to avoid the shorting of the individual connections on the wafer, and to control the size and location of voids in the solder upon solidification.

Semiconductor wafer with circuits bonded to a substrate

A field effect transistor is described incorporating a semiconductor layer over a layer or substrate of semi-insulating semiconductor material and a gate electrode which periodically passes through the semiconductor layer to the substrate to form a plurality of conducting bars in the semiconductor layer for transistor current and which at pinch-off confines the current interior of each conducting bar. The invention overcomes the problem of leakage current at pinch-off, thus improving the efficiency of the field effect transistor as a power amplifier.

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Sykesville, MD, United States of America

Rowland C Clarke