Stmicroelectronics (crolles 2) Sas

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Rossella Ranica

Pascale Mazoyer

Alexandre Villaret

Olivier Weber

Pierre Malinge

Nicolas Planes

The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg&#x2212;0.04&#x2212;0.005*Xge&#x3c;Wf1&#x3c;Wfmg&#x2212;0.03&#x2212;0.005*Xge.

Transistors with various levels of threshold voltages and absence of distortions between nMOS and pMOS

A memory cell with one MOS transistor formed in a floating body region isolated on its lower surface by a junction. A region of the same conductivity type as the floating body region but more heavily doped than said region is arranged under the drain region of the MOS transistor.

Memory cell comprising one MOS transistor with an isolated body having an improved read sensitivity

A memory cell with one transistor on a floating body region isolated by its lower surface by a junction. According to the present invention, the junction is non-planar and, for example, includes a protrusion directed towards the transistor surface.

Memory cell comprising one MOS transistor with an isolated body having a reinforced memory effect

A dynamic random access memory (DRAM) including memory cells distributed in rows and in columns, each memory cell comprising a MOS transistor with a floating body, the memory comprising circuitry for writing a datum into a determined (i.e. selected) memory cell belonging to a determined (i.e. selected) row and to a determined (i.e. selected) column, wherein the write circuitry comprises circuitry capable of bringing the drains of the memory cells of the determined column to a voltage V; circuitry capable of bringing the sources of the memory cells of the determined row to a voltage V; and circuitry capable of bringing the drains of the memory cells of the columns other than the determined column and the sources of the memory cells of the rows other than the determined row to a voltage V, voltages V, V, and Vbeing such that |V&#x2212;V|&#x3e;|V&#x2212;V| and (V&#x2212;V)&#xd7;(V&#x2212;V)&#x3e;0.

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Grenoble, France

Rossella Ranica