Xilinx, Inc.

Nvidia Corporation

Ronilo Boja

Inderjit Singh

Abraham Fong Yee

Teckgyu Kang

Leilei Zhang

Kumar Nagarajan

Zuhair Bokharey

Nael Zohni

Chandan Bhat

Gerilyn Maloney

A chip package and method for fabricating the same are provided which utilize a cover having one or more windows formed through one or more sidewalls to provide excellent resistance to warpage while allowing access to an internal volume of the chip package. In one example, the chip package includes a package substrate, an integrated circuit (IC) die, and a cover disposed over the IC die. The cover includes a lower surface facing the IC die, an upper surface facing away from the IC die, a lip extending from the lower surface, and a first sidewall extending from a first edge of the upper surface to the bottom of the lip. The lip is secured to the package substrate and encloses a volume between the lower surface and the package substrate. The IC die resides in the volume. A first elongated window is formed through the first sidewall and exposes the volume through the cover.

Chip package having a cover with window

A chip package assembly and method for fabricating the same are provided which utilize a composite stiffener selected to provide excellent resistance to warpage without detrimentally imposing excessive stress on a package substrate of the package assembly. In one example, the chip package assembly includes an integrated circuit die stacked on a top surface of a package substrate, and a composite stiffener coupled to a first edge of the package substrate. The composite stiffener includes a first stiffener member and a second stiffener member. The first stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member is disposed over the first stiffener member. The second stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member has a Young's modulus that is less than a Young's modulus of the first stiffener member.

Chip package assembly with composite stiffener

A chip package assembly, a package substrate and methods for fabricating the same are disclosed herein. In one example, a chip package assembly includes a package substrate, an IC die and a stiffener. The package substrate includes a first dam projecting from a top surface of the package substrate. The IC die and the stiffener are mounted to the top surface of the package substrate. The stiffener includes a bottom surface that is disposed adjacent to the first dam. At least one surface mounted component is mounted to a region of the package substrate defined between the stiffener and the IC die. An adhesive coupling the stiffener to the package substrate is in contact with the first dam.

Chip package assembly with surface mounted component protection

A process for manufacturing a printed circuit board having high-density microvias formed in a thick substrate is disclosed. The method includes the steps of forming one or more holes in a thick substrate using a laser drilling technique, electroplating the one or more holes with a conductive material, wherein the conductive material does not completely fill the one or more holes, and filling the one or more plated holes with a non-conductive material.

Process for manufacturing a printed circuit board having high density microvias formed in a thick substrate

A system, method, and computer program product are provided for producing a cavity bottom package of a package-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer including a first set of pads configured to be electrically coupled to a second set of pads of an integrated circuit die. A layer of non-conductive material is applied to the top layer of the bottom package and a cavity is formed in the layer of non-conductive material to expose the first set of pads, where the cavity is configured to contain the integrated circuit die oriented such that the second set of pads face the first set of pads.

System, method, and computer program product for a cavity package-on-package structure

Integrated circuit packaging devices and methods are disclosed. An embodiment package lid is formed from a single piece of material. The lid includes a planar rectangular main body having a bottom surface, and a leg disposed at each corner of the main body and within a perimeter of the main body. Each leg has a wall projecting downwardly from the main body and a non-planar bottom surface disposed at a bottom of the wall. The non-planar bottom surface of the leg faces a same direction as the main body bottom surface.

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Gilroy, CA, United States of America

Ronilo Boja