Applied Materials, Inc.

Rongjun Wang

Xianmin Tang

Chi Hong Ching

Muhammad M Rasheed

Xiaodong Wang

Mahendra Pakala

Lin Xue

Anantha K Subramani

Daniel Lee Diehl

Hua Chung

Tza-Jing Gung

Mingwei Zhu

Vivek Agrawal

Nag B Patibandla

Keith A Miller

Jianxin Lei

Zhendong Liu

Jaesoo Ahn

Srinivas Gandikota

Yong Cao

Adolph Miller Allen

Thanh X Nguyen

Nirmalya Maity

Fuhong Zhang

Jick M Yu

Wei Lei

Hanbing Wu

Aixi Zhang

John C Forster

Kirankumar Neelasandra Savandaiah

Praburam Gopalraja

Lara Hawrylchak

Yixiong Yang

Yu Lei

Renu Whig

Martin Lee Riker

Christophe Marcadal

Joung Joo Lee

Yi Xu

William Fruchterman

Shouyin Zhang

Daniel John Hoffman

Xinyu Fu

Cheng-Hsiung Matt Tsai

Sahil Patel

Omkaram Nalamasu

John Pipitone

Weimin Zeng

Lei Zhou

Liqi Wu

Ashish Goel

Tsung-Han Yang

Yana Cheng

Jie Zhang

Nobuyuki Sasaki

Wenting Hou

Irena H Wysok

Dinesh Saigal

Halbert Chong

Mei Yin Chang

Wei W Wang

Mark Joseph Saly

Khoi A Phan

Feng Quan Liu

Michael Santiago Cox

Bhaskar Jyoti Bhuyan

Dien-Yeh Wu

Wei D Wang

Huixiong Dai

Naomi Yoshida

Alan A Ritchie

Christopher S Ngai

Wei V Tang

Zhenbin Ge

Xiangjin Xie

Shih Chung Chen

Hong Sheng Yang

Tao Huang

Sang-Ho Yu

Donny Young

Kevin Kashefi

Tingjun Xu

Lin Dong

Jiang Lu

David Michael Thompson

Srinivas Guggilla

Cong Trinh

Shirish A Pethe

Yongjing Lin

Ryan Hanson

Steven C Hung

Aravind Kamath

Maurice E Ewert

Anthony Chih-Tung Chan

Mukund Sundararajan

Zhigang Xie

Deepak Jadhav

Karla M Bernal Ramos

Chih-Hsun Hsu

Tiefeng Shi

Embodiments of the disclosure relate to methods for metal gapfill of a logic device with lower resistivity. Specific embodiments provide integrated separate tungsten PVD processes with plasma-etch to solve the overhang issue caused by tungsten PVD and the high resistivity caused by nucleation.

Low resistivity gapfill for logic devices

Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.

Methods for forming structures with desired crystallinity for MRAM applications

Embodiments of the disclosure provide methods for forming MTJ structures from a film stack disposed on a substrate for MRAM applications and associated MTJ devices. The methods described herein include forming the film properties of material layers from the film stack to create a film stack with a sufficiently high perpendicular magnetic anisotropy (PMA). An iron containing oxide capping layer is utilized to generate the desirable PMA. By utilizing an iron containing oxide capping layer, thickness of the capping layer can be more finely controlled and reliance on boron at the interface of the magnetic storage layer and the capping layer is reduced.

Magnetic tunnel junctions with tunable high perpendicular magnetic anisotropy

A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl, MoCl) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.

Metal oxide preclean for bottom-up gapfill in MEOL and BEOL

A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

One chamber multi-station selective metal removal

Methods and apparatus reduce defects in substrates processed in a physical vapor (PVD) chamber. In some embodiments, a method for cleaning a process kit disposed in an inner volume of a process chamber includes positioning a non-sputtering shutter disk on a substrate support of the PVD chamber; energizing an oxygen-containing cleaning gas disposed in the inner volume of the PVD chamber to create a plasma reactive with carbon-based materials; and heating the process kit having a carbon-based material adhered thereto while exposed to the plasma to remove at least a portion of the carbon-based material adhered to the process kit.

Shutter disk for physical vapor deposition (PVD) chamber

Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.

Methods for forming metal gapfill with low resistivity

Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.

Selective metal removal with flowable polymer

Magnet assemblies comprising a housing with a top plate each comprising aligned openings are described. The housing has a bottom ring and an annular wall with a plurality of openings formed in the bottom ring. The top plate is on the housing and has a plurality of openings aligned with the plurality of openings in the bottom ring of the housing. The magnet assembly may also include a non-conducting base plate and/or a conductive cover plate. Methods for using the magnet assembly and magnetic field tuning are also described.

Top magnets for decreased non-uniformity in PVD

Methods and apparatus for processing substrates are disclosed. In some embodiments, a process chamber for processing a substrate includes: a body having an interior volume and a target to be sputtered, the interior volume including a central portion and a peripheral portion; a substrate support disposed in the interior volume opposite the target and having a support surface configured to support the substrate; a collimator disposed in the interior volume between the target and the substrate support; a first magnet disposed about the body proximate the collimator; a second magnet disposed about the body above the support surface and entirely below the collimator and spaced vertically below the first magnet; and a third magnet disposed about the body and spaced vertically between the first magnet and the second magnet. The first, second, and third magnets are configured to generate respective magnetic fields to redistribute ions over the substrate.

Methods and apparatus for controlling ion fraction in physical vapor deposition processes

Methods and apparatus for processing a substrate are provided herein. For example, a processing chamber for processing a substrate comprises a sputtering target, a chamber wall at least partially defining an inner volume within the processing chamber and connected to ground, a power source comprising an RF power source, a process kit surrounding the sputtering target and a substrate support, an auto capacitor tuner (ACT) connected to ground and the sputtering target, and a controller configured to energize the cleaning gas disposed in the inner volume of the processing chamber to create the plasma and tune the sputtering target using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit during the etch process to remove sputtering material from the process kit, wherein the predetermined potential difference is based on a resonant point of the ACT.

Methods and apparatus for processing a substrate

Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

Silicon-containing layer for bit line resistance reduction

Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

Oxygen controlled PVD ALN buffer for GAN-based optoelectronic and electronic devices

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Dublin, CA, United States of America

Rongjun Wang