Infineon Technologies Ag

Siemens Aktiengesellschaft

Siemens Aktiengesellscaft

Ronald Kakoschke

Thomas Nirschl

Georg Tempel

Klaus Schruefer

Helmut Horst Tews

Danny Shum

Franz Schuler

Wolfgang Gruber

Dominik Wegertseder

Danny Pak-Chum Shum

Doris Schmitt-Landsiedel

Klaus Schrüfer

Thomas Schweizer

Josef Willer

Holger Sedlak

Thomas Schulz

Harald Seidl

Armin Tilke

Christian Pacha

Juergen Holz

Martin Stiftinger

Laura Pescini

Regina Stokan

Karl Robert Strenz

Berndt Gammel

Gerd Dirscherl

Stefan Rueping

Wolfram Langheinrich

Andreas Kux

John Power

Philip Schlazer

Gunther Plasa

Thomas Schwelzer

Helga Braun

A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.

Methods for producing a tunnel field-effect transistor

One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.

Semiconductor device and method of making semiconductor device

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor

A memory element includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.

Semiconductor device including FinFET device

A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.

Methods for fabricating an integrated circuit arrangement comprising isolating trenches and a field effect transistor

An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD) in comparison with other transistors (T) on the same integrated circuit arrangement (). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D, S) of the tunnel field effect transistor.

One or more embodiments relate to a memory device, comprising: a memory element; and a FinFET select device including a fin, a gate line supported by the fin, and a contact element coupled between a surface of the fin and the memory element, the contact element being in direct contact with a top surface of the fin.

Apparatus of memory array using FinFETs

A method for fabricating a field-effect transistor is provided. The method includes forming a substrate region, forming two terminal regions at the substrate region, one terminal region being a source region and the other terminal region being a drain region, forming two electrically insulating insulating layers, which are arranged at mutually opposite sides of the substrate region and are adjoined by control regions, forming an electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region the conductive connecting region comprising a metal-semiconductor compound, leveling a surface by chemical mechanical polishing after forming the control regions, etching-back the control regions after polishing, and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region.

Method for producing an integrated field-effect transistor

A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.

Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns

A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.

Integrated memory device having columns having multiple bit lines

Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.

Deep trench isolation structures and methods of formation thereof

One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope.

Memory device comprising select gate including carbon allotrope

A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

Growing community of inventors

Munich, Germany

Ronald Kakoschke