International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Advanced Micro Devices Corporation

Globalfoundries U.S. 2 LLC

Auriga Innovations, Inc

Ronald G Filippi

Ping-Chuan Wang

Andrew Herbert Simon

Griselda Bonilla

Naftali Eliahu Lustig

Samuel S Choi

Kaushik Chanda

Junjing Bao

Stephan Grunow

Erdem Kaltalioglu

Lijuan Zhang

Wai-Kin Li

Chih-Chao Yang

Roy Charles Iggulden

Elbert Emin Huang

Andrew Tae Kim

Lawrence Alfred Clevenger

Theodorus E Standaert

Timothy Dooling Sullivan

Edward William Kiewra

Paul Stephen McLaughlin

Sujatha Sankaran

Kenneth Parker Rodbell

John Anthony Fitzsimmons

Thomas W Dyer

Thomas M Shaw

Stephen Edward Greco

James A Culp

Chao-Kun Hu

Hazara Singh Rathore

Matthew S Angyal

Jason Paul Gill

Jeffrey P Gambino

Baozhen Li

Hanyi Ding

Yun-Yu Wang

Tom C Lee

James J Demarest

Du Binh Nguyen

Birendra N Agarwala

Richard Andre Wachnik

Andrew P Cowley

Robert Daniel Edwards

Jong-Ru Guo

Daniel C Edelstein

Xiao Hu Liu

Vincent James McGahay

Dan Moy

Joseph M Lukaitis

Kevin W Kolvenbach

Stefan Weber

Samuel S S Choi

Kaushik Chandra

Jack Allan Mandelman

Dureseti Chidambarrao

Bucknell Chapman Webb

Conal Eugene Murray

David Lee Rath

Shahab Siddiqui

Takamasa Usui

Robert Rosenberg

Lynne Marie Gignac

Mark Hoinkis

Tomio Katata

Patrick William Dehaven

Cathryn Jeanne Christiansen

Herbert Palm

Charles C Goldsmith

Tibor Bolom

Rainer Florian Schnabel

James R Lloyd

Florian Schnabel

Richard G Smith

Stephen K Loh

Samuel Sung Shik Choi

Chunyan E Tian

Chi-Hua Yang

Hideaki Aochi

Hans W Poetzlberger

James D Werking

Alexander J Swinton

Phillip C Lin

James Joseph Poulin

Kevin H Brelsford

Edward W Kiewara

Wai-Lin Li

Robert D Raviart

Jeffery L Hurd

Ebrahim A Mehter

Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Wafer rigidity with reinforcement structure

Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.

Interconnect structure having subtractive etch feature and damascene feature

A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Stacked via structure for metal fuse applications

A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

Forming air gap

A method of forming an integrated metal line and interconnect. The method may include forming a first trench in a first ILD exposing a lower metal line, the first ILD is above a substrate, and the lower metal line is in the substrate; forming a first barrier layer in the first trench; forming an integrated metal layer (including a first metal line and a first via) on the first barrier layer; forming a first hardmask on the integrated metal layer; forming an isolation trench in the first hardmask and in the first metal line; forming a second barrier layer in the isolation trench; removing a portion of the second barrier layer from a bottom of the isolation trench exposing the first ILD; and forming a second ILD on the second barrier and in the isolation trench, where a bottom of the second ILD is in the first ILD.

Subtractive etch interconnects

A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

Detecting a void between a via and a wiring line

A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Back-end electrically programmable fuse

Interconnect structure having substractive etch feature and damascene feature

The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

Interconnect reliability structures

Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive lines. Multiple seed layer deposition steps or variable trench bottom areas are used to locally control the dopant concentration within the interconnect structures at the same wiring level, which provides a robust integration approach for metallizing interconnects in future-generation technology nodes.

Interconnect structures with variable dopant levels

A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.

TSV deep trench capacitor and anti-fuse structure

An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Interconnect structure with enhanced reliability

Growing community of inventors

Wappingers Falls, NY, United States of America

Ronald G Filippi