Stats Chippac Pte. Ltd.

Advanpack Solutions Pte Ltd.

Romeo Emmanuel P Alvarez

Yaojian Lin

Byung Tai Do

Il Kwon Shim

Haijing Cao

Sheila Marie L Alvarez

Wan Lay Looi

Tan Kim Hwee

An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads.

Integrated circuit system having different-size solder bumps and different-size bonding pads

An integrated circuit package system includes an integrated circuit, and forming a patterned redistribution pad over the integrated circuit.

Integrated circuit package system with bump pad

Integrated circuit solder bumping system

A method for solder bumping provides a substrate and forms a film on the substrate. The film has openings therethrough. A stencil is aligned on the film. The stencil has openings therethrough over the openings through the film. Solder paste is printed onto the substrate and into the openings through the stencil and the openings through the film. The solder paste is reflowed to form solder balls therefrom. The stencil and the film are then removed.

Method for solder bumping, and solder-bumping structures produced thereby

A method of manufacturing a semiconductor package includes providing a substrate having a plurality of contacts with solder bump contact areas that are unmasked. A plurality of underfill bumps is formed on the plurality of contacts selectively in the solder bump contact areas. A die having a plurality of solder bumps is positioned on the substrate so the plurality of solder bumps is substantially vertically aligned with the plurality of underfill bumps. The plurality of solder bumps is pressed into the plurality of underfill bumps until the plurality of solder bumps contacts the plurality of contacts. The plurality of solder bumps is reflowed. The die, the plurality of solder bumps, and the plurality of contacts are encapsulated to expose a lower surface of the plurality of contacts.

Semiconductor package with selective underfill and fabrication method therfor

A method for fabricating a chip scale package is described. The method utilizes wafer level processes to obtain a chip level package. The method particularly avoids the use of mechanical grinding by the novel use of molding, extruding, and etching technology.

Method for forming a wafer level chip scale package, and package formed thereby

An oxidized ( ) copper leadframe and a semiconductor die with copper posts extending from die pads, and with solder balls coated ( ) with flux on the end of the copper posts, are provided. The semiconductor die is placed ( ) on the oxidized copper leadframe, with the solder balls abutting portions of the layer of oxide, above and aligned with, interconnect locations on the leadframe. When reflowed ( ), the flux on the abutting portions of the oxide layer selectively cleans these portions of the oxide layer, away from the interconnect locations. In addition, the solder balls change to molten state and adhere to the cleaned copper surfaces at the interconnect locations. Advantageously, the rest of the oxide layer that is not cleaned away provides a passivation layer that advantageously contains and prevents the molten solder from flowing away from the interconnect locations.

Growing community of inventors

Singapore, Singapore

Romeo Emmanuel P Alvarez