Applied Materials Israel Limited

Roman Kris

Ishai Schwarzband

Shimon Levi

Vadim Vereschagin

Grigory Klebanov

Yakov Weinberg

Einat Frishman

Sharon Duvdevani-Bar

Dhananjay Singh Rathore

Elad Sommer

Ran Goldman

Rafael Bistritzer

Ofer Adan

Ilan Ben-Harush

Sahar Levin

Itay Zauer

Olga Novak

Ron Naftali

Haim Feldman

Boaz Cohen

Silviu Reinhorn

Doron Girmonsky

Ariel Shkalim

Moshe Langer

Sergey Khristo

Evgeny Bal

Yan Avniel

Mor Baram

Efrat Noifeld

Dan Grossman

Assaf Shamir

Jannelle Anna Geva

Chih-Chieh Chang

Yan Ivanchenko

Ori Shoval

Gal Daniel Gutterman

Daniel Alan Rogers

Dan Lange

Arbel Englander

Ishai Schwartzband

Ido Friedler

Tal Orenstein

Meir Vengrover

Noa Marom

Avi Aviad Ben Simhon

Jitendra Pradipkumar Chaudhary

Ran Alkoken

Meng Li Cecilia Lim

Roi Meir

Hiroshi Miroku

Kasturi Saha

Taku Yoshizawa

Arundeepth Thamarassery

Omer Kerem

Asaf Golov

A system of examination of a semiconductor specimen, comprising a processor and memory circuitry (PMC) configured to:

Examination of a hole formed in a semiconductor specimen

Input data may be received. The input data may include an image of a pattern and location data that identifies a modified portion of the pattern. A processing device may determine a first parameter of a first dimension within the pattern and a second parameter of a second dimension outside of the pattern. A combined set may be generated based on the first parameter and the second parameter. A defect associated with the modified portion may be classified based on the combined set.

Determining a critical dimension variation of a pattern

There is provided a system and method of a method of detecting a local shape deviation of a structural element in a semiconductor specimen, comprising: obtaining an image comprising an image representation of the structural element; extracting, from the image, an actual contour of the image representation; estimating a reference contour of the image representation indicative of a standard shape of the structural element, wherein the reference contour is estimated based on a Fourier descriptor representative of the reference contour, the Fourier descriptor being estimated using an optimization method based on a loss function specifically selected to be insensitive to local shape deviation of the actual contour; and performing one or more measurements representative of one or more differences between the actual contour and the reference contour, the measurements indicative of whether a local shape deviation is present in the structural element.

Local shape deviation in a semiconductor specimen

A method for process control of a semiconductor structure fabricated by a series of fabrication steps, the method comprising obtaining an image of the semiconductor structure indicative of at least two individual fabrication steps; wherein the image is generated by scanning the semiconductor structure with a charged particle beam and collecting signals emanating from the semiconductor structure; and processing, by a hardware processor, the image to determining a parameter of the semiconductor structure, wherein processing includes measuring step/s from among the fabrication steps as an individual feature.

Method, system and computer program product for 3D-NAND CDSEM metrology

A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.

Evaluating an intermediate product related to a three-dimensional NAND memory unit

There is provided a system and method of performing a measurement with respect to an epitaxy formed in a finFET, the epitaxy being separated with at least one adjacent epitaxy by at least one HK fin. The method comprises obtaining an image of the epitaxy and the at least one HK fin, and a gray level (GL) profile indicative of GL distribution of the image; detecting edges of the at least one HK fin; determining two inflection points of the GL profile within an area of interest in the image; performing a critical dimension (CD) measurement between the two inflection points; determining whether to apply correction to the CD measurement based on a GL ratio indicative of a relative position between the epitaxy and the at least one HK fin; and applying correction to the CD measurement upon the GL ratio meeting a predetermined criterion.

Epitaxy metrology in fin field effect transistors

There is provided a system and method of generating a metrology recipe usable for examining a semiconductor specimen, comprising: obtaining a first image set comprising a plurality of first images captured by an examination tool, obtaining a second image set comprising a plurality of second images, wherein each second image is simulated based on at least one first image, wherein each second image is associated with ground truth data; performing a first test on the first image set and a second test on the second image set in accordance with a metrology recipe configured with a first parameter set, and determining, in response to a predetermined criterion not being met, to select a second parameter set, configure the metrology recipe with the second parameter set, and repeat the first test and the second test in accordance with the metrology recipe configured with the second parameter set.

Generating a metrology recipe usable for examination of a semiconductor specimen

An improved technique for determining height difference in patterns provided on semiconductor wafers uses real measurements (e.g., measurements from SEM images) and a height difference determination model. In one version of the model, a measurable variable of the model is expressed in terms of a function of a change in depth of shadow (i.e. relative brightness), wherein the depth of shadow depends on the height difference as well as width difference between two features on a semiconductor wafer. In another version of the model, the measurable variable is expressed in terms of a function of a change of a measured distance between two characteristic points on the real image of a periodic structure with respect to a change in a tilt angle of a scanning electron beam.

Measuring height difference in patterns on semiconductor wafers

A captured image of a pattern and a reference image of the pattern may be received. A contour of interest of the pattern may be identified. One or more measurements of a dimension of the pattern may be determined for each of the reference image and the captured image with respect to the contour of interest of the pattern. A defect associated with the contour of interest may be classified based on the determined one or more measurements of the dimension of the pattern for each of the reference image and the captured image.

An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.

Evaluating a hole formed in an intermediate product

A method for monitoring a first nanometric structure formed by a multiple patterning process, the method may include performing a first plurality of measurements to provide a first plurality of measurement results; wherein the performing of the first plurality of measurements comprises illuminating first plurality of locations of a first sidewall of the first nanometric structure by oblique charged particle beams of different tilt angles; and processing, by a hardware processor, the first plurality of measurement results to determine a first attribute of the first nanometric structure.

Method for monitoring nanometric structures

A method for determining overlay between layers of a multilayer structure may include obtaining a given image representing the multilayer structure, obtaining expected images for layers of the multilayer structure, providing a combined expected image of the multilayer structure as a combination of the expected images of said layers, performing registration of the given image against the combined expected image, and providing segmentation of the given image, thereby producing a segmented image, and maps of the layers of said multilayered structure. The method may further include determining overlay between any two selected layers of the multilayer structure by processing the maps of the two selected layers together with the expected images of said two selected layers.

Technique for measuring overlay between layers of a multilayer structure

A Critical Dimensions Scanning Electron Microscope (CD-SEM) is described that comprises a unit for performing CD-SEM measurements of a semiconductor wafer, a BSE imaging unit for obtaining a Grey Level image (GL) of the wafer, and a unit for GL analysis and for processing the GL analysis results with reference to results of the CD-measurements.

CD-SEM technique for wafers fabrication control

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Jerusalem, Israel

Roman Kris