Fab-Tech Incorporated

Roman J Hamerski

Walter Riley Buchanan

Wayne A Smith

Gary W Gladish

A high voltage electrical device ( ), having a substrate layer ( ), base layer ( ) and top layer ( ), provides high voltage properties in excess of 1000V. Slicing a wafer ( ) from an ingot ( ) created in by monocrystalline growth forms the substrate layer ( ), and this high quality crystal is used as the high resistivity layer in the device ( ). The base layer ( ) is a highly doped, low resistivity, epitaxial layer deposited on the lower surface ( ) of the substrate layer ( ) at a fast rate greater than approximately 2 microns/minute. The top layer ( ) is a diffusion layer diffused into an upper surface ( ) of the substrate layer ( ). To control stress in the wafer ( ), the epitaxial base is doped with germanium.

Method of manufacturing a device with epitaxial base

The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. During production, the low conductivity region has one surface that is etched before a high conductivity region is diffused into it or epitaxially deposited on it.

Apparatus and method for fabricating a high reverse voltage semiconductor device

The present invention is directed to a novel semiconductor device, which can be efficiently fabricated for use in Zener diode applications. Precision Zener diodes and the method for manufacturing the same are provided. The Zener diodes of the present invention are made from a semiconductor substrate layer having a range or resistivity, on which is grown an epitaxial layer. The epitaxial layer has a resistivity greater than that of the substrate. The diode also has an interior region of doped semiconductor material of the same conductivity type as the substrate. The interior region extends through the epitaxial layer and into the substrate layer. The diode also has a junction layer of a conductivity type different from the substrate. The junction layer is formed in the epitaxial surface, and the junction layer forms an interior P/N junction with the interior region and a peripheral P/N junction with a peripheral portion of the device. An additional device can optionally be produced in which a low contact resistance layer is implanted into an exterior surface of the junction layer.

Precision Zener diodes

A diode ( ), having first and second conductive layers ( ), a conductive pad ( ), and a distributed reverse surge guard ( ), provides increased protection from reverse current surges. The surge guard ( ) includes an outer loop ( ) of P -type surge guard material and an inner grid ( ) of linear sections ( ) which form a plurality of inner loops extending inside the outer loop ( ). The surge guard ( ) distributes any reverse current over the area of the conductive pad ( ) to provide increased protection from transient threats such as electrostatic discharge (ESD) and during electrical testing.

Distributed reverse surge guard

An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N material while the high resistivity layer can be an N layer. The buried dopant region can be of P material, thus forming a PN junction with an associated charge depletion zone in the N layer and an associated low reverse leakage current. The location of the P material allows for a full Schottky barrier between the N material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.

Method of manufacturing a schottky device

An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process. Once the predetermined pattern of dopant material is formed or otherwise deposited upon the upper surface of the epitaxial layer, the substrate, epitaxial and top layers are heated to form a diffusion region in the epitaxial layer, this diffusion region having a specific correlation to the predetermined pattern of dopant material. Once heated, the remaining top layer of dopant material is removed and the resultant substrate and diffused epitaxial layer is divided so as to form a plurality of separate electrical devices. Each patch of dopant material corresponds to the middle portion of an individual electrical device devisable from the resultant substrate and defused based and the diffusion region achieved by the heating process will be deepest substantially towards the middle portion of each respective electrical device and will be comparatively shallower at the edges of each such electrical device.

Method for making high voltage device

An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant, material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process. Once the predetermined pattern of dopant material is formed or otherwise deposited upon the upper surface of the epitaxial layer, the substrate, epitaxial and top layers are heated to form a diffusion region in the epitaxial layer, this diffusion region having a specific correlation to the predetermined pattern of dopant material. Once heated, the remaining top layer of dopant material is removed and the resultant substrate and diffused epitaxial layer is divided so as to form a plurality of separate electrical devices. Each patch of dopant material corresponds to the middle portion of an individual electrical device devisable from the resultant substrate and defused based and the diffusion region achieved by the heating process will be deepest substantially towards the middle portion of each respective electrical device and will be comparatively shallower at the edges of each such electrical device.

High voltage device and method

Schottky device

High voltage device and method for making the same

A single step etched moat ( ), having a regular grid work mask ( ) of mesa shields ( ) and edge termination shields ( ), is utilized to form, in a single etching step, semiconductor devices ( ) having lengthy edge terminations for reduced edge termination failure. The desired semiconductor devices ( ) include a high resistivity, monocrystalline grown substrate layer ( ), a low resistivity epitaxial base layer ( ), and a low resistivity top layer ( ). The regular grid work of mesa shields ( ) and edge termination shields ( ) define open grid lines ( ) and open grid rings ( ). The open grid lines ( ) are wider than the open grid rings ( ), so that as the moats ( ) are etched, a deeper grid line divot ( ) is formed below the open grid lines ( ) and a more shallow grid ring divot is formed below the open grid ring ( ).

Growing community of inventors

Olathe, KS, United States of America

Roman J Hamerski