Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics (Crolles 2) Sas

Stmicroelectronics Gmbh

Stmicroelectronics S.a.

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique

Université´ D'aix-Marseille

Romain Wacquez

Maud Vinet

Laurent Grenouillet

Philippe Coronel

Yannick Le Tiec

Nicolas J Loubet

Sylvain Maitrejean

Yves Morand

Jessy Bustos

Thomas Skotnicki

Shay Reboh

Jean-Michel Hartmann

Damien Lenoble

Florian Pebay-Peyroula

Christophe Constancias

Jean-Michel Portal

Mikael Carmona

Jean Coignus

Sylvie M Mignot

Rodolphe Heliot

Jacques Fournier

Robin Cerutti

Olivier Faynot

Xavier Jehl

Mikaël Carmona

Vincent Destefanis

Vincenzo Della Marca

Alexis Krakovinsky

Marc Bocquet

Carlo Reita

Marc Sanquer

Licinius-Pompiliu Benea

Emanuele Valea

The present description concerns a random number generation circuit () of correlated sampling ring oscillator type comprising: two identical ring oscillators (RO, R) implemented in CMOS-on-FDSOI technology; a circuit () sampling and storing an output (O) of one of the two oscillators (RO) at a frequency of the other one of the two oscillators (RO) and delivering a corresponding binary signal (Beat); and a circuit () controlling back gates of PMOS and NMOS transistors of at least one delay element of at least one of the two oscillators (RO, RO) based on a period difference between the two oscillators (RO, RO).

Coherent sampling true random number generation in FD-SOI technology

A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.

Process for producing FET transistors

A method is provided for modifying a strain state of a block of a semiconducting material having a crystalline structure, including steps in the following order: a) forming an amorphous lower region in the block of semiconducting material resting on a substrate amorphous, while maintaining the crystalline structure of an upper region of the block, which is in contact with the lower region; b) performing at least one creep annealing of the block with a suitable duration and temperature so that creep occurs in the lower region and without recrystallizing the material of this lower region; and c) performing at least one recrystallization annealing of the lower region of the block.

Method for modifying the strain state of a block of a semiconducting material

A method for forming a non-volatile memory cell intended to switch the memory cell from an unformed state to a formed state, the memory cell including an ordered stack of a lower electrode, a layer of insulating material and an upper electrode. The forming method includes a breakdown operation in which at least one laser shot is emitted towards the layer of insulating material to make the layer of insulating material active by making it pass from a high resistance state to a low resistance state, the memory cell being formed when the layer of insulating material is active.

Method for forming a non-volatile memory cell, non-volatile memory cell formed according to said method and microelectronic device comprising such memory cells

Electronic device having a physical unclonable function identifier

A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.

Method for manufacturing a fin MOS transistor

The invention provides a method of etching a crystalline semiconductor material (), the method being characterized in that it comprises: at least one ion implantation performed by implanting a plurality of ions () in at least one volume () of the semiconductor material () in such a manner as to make the semiconductor material amorphous in the at least one implanted volume (), and as to keep the semiconductor material () in a crystalline state outside () the at least one implanted volume (); and at least one chemical etching for selectively etching the amorphous semiconductor material relative to the crystalline semiconductor material, so as to remove the semiconductor material in the at least one volume () and so as to keep the semiconductor material outside () the at least one volume ().

Method of etching a crystalline semiconductor material by ion implantation and then chemical etching based on hydrogen chloride

Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

Method to co-integrate oppositely strained semiconductor devices on a same substrate

A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, &#x2014;filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

Method for fabricating microelectronic devices with isolation trenches partially formed under active regions

A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.

A method of producing a microelectronic device in a substrate including a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, the method including: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device; chemical vapor etching the second semiconductor layer, at a level of a bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region; filling the trench and the etched part of the second semiconductor layer with a dielectric material.

Method of producing a microelectronic device in a monocrystalline semiconductor substrate with isolation trenches partially formed under an active region

A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.

The present invention relates to a method for chemically treating the surface condition of a silicon substrate for the roughness contrast characterized in that it comprises at least two successive treatment cycles, with each treatment cycle comprising a first step including placing in contact the silicon substrate with a first solution containing water diluted hydrofluoric (HF) acid and then a second step carried out at a temperature of less than 40&#xb0; C., comprising placing in contact the silicon layer with a second solution containing water (HO) diluted ammonium hydroxide (NHOH) and hydrogen peroxide (HO), in order to obtain a roughness of less than 0.100 nanometer on a 1 &#x3bc;m&#xd7;1 &#x3bc;m area upon completion of the treatment cycles. The invention will be applied in the field of microelectronics for the production of transistors, of surfaces for photovoltaic panels or for direct molecular bonding.

Method for treating the surface of a silicon substrate

A microelectronic device is provided, including: a substrate including a first semiconductor layer positioned on a dielectric layer and a second semiconductor layer; and an isolation trench disposed through the first semiconductor layer, the dielectric layer, and a part of the thickness of the second semiconductor layer, including a dielectric material and delimiting, in the first semiconductor layer, a roughly rectangular active area of the device, wherein in said part of the thickness of the second semiconductor layer, at least one portion of the dielectric material is positioned under the active area delimited by at least four side walls of the trench, and two of the at least four side walls are roughly parallel with one another and are positioned under the active area, and the other two of the at least four side walls are orthogonal to said two walls and are not positioned under the active area.

Microelectronic device with isolation trenches extending under an active area

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Marseilles, France

Romain Wacquez