Fairchild Semiconductor Corporation

Rohit Dikshit

Michael D Gruenhagen

Joseph Andrew Yedinak

Chung-Lin Wu

James J Murphy

Christopher Lawrence Rexer

Mark L Rinehimer

Ihsiu Ho

Fred Session

Suku Kim

Eddy Tjhia

Dan Kinzer

Mark Larsen

Ritu Sodhi

Tracie Petersen

This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

Double layer metal (DLM) power MOSFET

Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described.

Semiconductor die containing lateral edge shapes and textures

Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same

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Herriman, UT, United States of America

Rohit Dikshit