Northrop Grumman Systems Corporation

Trw Limited

Roger S Tsai

Michael Edward Barsky

Richard Lai

Ronald W Grundbacher

Weidong Liu

Mark Kintis

Robert Coffie

Yaochung Chen

Po-Hsin Liu

Xianglin Zeng

Ioulia Smorchkova

Carol Osaka Namba

Yeong-Chang Chou

Michael D Lange

Shih-En Shih

Philip W Hon

Sumiko L Poust

Jose G Padilla

Peter S Nam

A semiconductor device is provided that comprises a base structure, a first channel layer overlying the base structure, a second channel layer overlying the first channel layer, and first, second, and third ohmic contacts overlying the second channel layer. The semiconductor device further comprises a metal-semiconductor heterodimension field effect transistor that is formed between the first and second ohmic contacts, the metal-semiconductor heterodimension field effect transistor including a first gate formed through the first and second channel layers. The semiconductor device yet further comprises a high electron mobility transistor formed between the second and third ohmic contacts, the high electron mobility transistor including a second gate formed through the second channel layer without extending through the first channel layer.

Metal-semiconductor heterodimension field effect transistors (MESHFET) and high electron mobility transistor (HEMT) based device and method of making the same

An exemplary FET includes a substrate and multiple vertically stacked layer groups with each layer group having a quantum well semiconductive layer and a nonconductive layer adjacent the first quantum well semiconductive layer. Conductive source and drain electrodes in conductive contact with the semiconductive layers. A 3-dimensional ridge of the stacked layer groups is defined between spaced apart first and second trenches which are between the source and drain electrodes. A continuous conductive side gate is disposed on the sides and top of the ridge for inducing a field into the semiconductive layers. A gate electrode is disposed in conductive contact with the conductive side gate.

Multiple layer quantum well FET with a side-gate

An exemplary FET includes a base and first and second stacked layer groups each having a nonconductive layer and a semiconductive layer adjacent the nonconductive layer. Source and drain electrodes are in low resistance contact with the semiconductive layers. First and second parallel trenches extend vertically between the source and drain electrodes to create access to first and second edges, respectively, of the layers. A 3-dimensional ridge is defined by the layers between the first and second trenches. A continuous conductive side gate extends generally perpendicular to the trenches and engages the first edges, the top of the ridge and the second edges. A gate electrode is disposed in low resistance contact with the conductive side gate. The figure of merit for the FET increases as the number of layer groups increases. A plurality of parallel spaced apart ridges, all engaged by the same side gate, can be utilized.

Multiple layer side-gate FET switch

A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.

Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems

A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.

High electron mobility transistor semiconductor device having field mitigating plate and fabrication method thereof

Antimony-based semiconductor devices are formed over a substrate structure () that includes an antimony-based buffer layer () and an antimony-based buffer cap (). Multiple epitaxial layers () formed over the substrate structure () are dry etched to form device mesas () and the buffer cap () provides a desirably smooth mesa floor and electrical isolation around the mesas.

Method for etching mesa isolation in antimony-based compound semiconductor structures

A semi-physical device model for HEMTs that can represent known physical device characteristics and measured high frequency small signal characteristics relatively accurately. The semi-physical device model in accordance with the present invention uses analytical expressions to model the fundamental electric charge and field structure of a HEMT internal structure. These expressions are based on the device physics but are in empirical form. In this way, the model is able to maintain physical dependency with good fidelity while retaining accurate measured-to-modeled DC and small signal characteristics. The model in accordance with the present invention provides model elements for a standard small signal equivalent circuit model of FET. The model elements are derived from small signal excitation analysis of intrinsic charge and electric field as modeled within the device by the semi-physical HEMT model. As such, the RF performance can be predicted at arbitrary bias points.

Semi-physical modeling of HEMT high frequency small signal equivalent circuit models

A hybrid model formed from a semi-physical device model along with an accurate data-fitting model in order to implement a relatively accurate physical device model as a large signal microwave circuit computer-aided design (CAD) tool. The semi-physical device model enables accurate representation of known physical device characteristics and measured bias-dependent characteristics. This model is used to accurately simulate the effect of process variation and environmental changes on bias-dependent characteristics. The data-fitting model is used to model these characteristics with relatively good fidelity. The expressions of the model are constructed to be charge conservative. As such, the model is computationally robust within the harmonic balance algorithms employed by known large signal microwave circuit CAD tools.

Hybrid semi-physical and data fitting HEMT modeling approach for large signal and non-linear microwave/millimeter wave circuit CAD

A method of using bias-dependent S-parameter measurements as a form of microscopy. The microscopy can be used to resolve the details of the internal charge and electric field structure of a semiconductor device. Like other forms of microscopy, the S-parameter microscopy focuses on pseudo &ldquo;images&rdquo; and provides a contrast in the &ldquo;images&rdquo;. Essentially, the images are gathered in raw form as S-parameter measurements and extracted as small signal models. The models are used to form charge control maps, through a selective method analogous to focusing. Focusing is provided by an algorithm for the unique determination of small signal parameters with contrasts provided by utilizing measured bias dependent activity to discriminate boundaries between the electrical charge and fields. As such, the system is able to accurately forecast semiconductor performance.

S-parameter microscopy for semiconductor devices

A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.

Process for forming a large area, high gate current HEMT diode

A model for a semiconductor device and more particularly to a Pi-FET with multiple gate fingers. The model takes into account various parasitics and the inter-relationship therebetween. In particular, multi-finger Pi-FETs are modeled as multiple single finger unit cells. Each single unit cell takes into account off-mesa parasitics, inter-electrode parasitics, on-mesa parasitics and includes an intrinsic model which represents the physics that predominantly determine FET performance. As such, the model can be used for relativity accurate device technology modeling, optimization of device performance and device design.

Embedding parasitic model for pi-fet layouts

A single-layer, metal-insulator-metal capacitor, a monolithic microwave integrated circuit including such capacitors, and a process of fabricating such capacitors. The capacitor has a single layer of insulating material between two metallic layers. At least one of the metallic layers has rounded corners, reducing the electric field at the corners, and so lessening the likelihood of breakdown. In one preferred embodiment, each metal layer has rounded corners. The capacitors can be fabricated by an optical lithographic process.

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Torrance, CA, United States of America

Roger S Tsai