Texas Instruments Corporation

Other

Roger A Haken

Thomas C Holloway

Che-Chia Wei

Thomas E Tang

Howard L Tigelaar

Donald J Coleman, Jr

Richard A Chapman

Clarence W Teng

Robert Groover, Iii

David A Bell

David Barry Scott

James L Paterson

Robert H Havemann

Robert H Eklund

Larry R Hite

Chi K Lau

Chung S Wang

Michael E Alperin

William E Feger

A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealing, the source/drain regions have graded regions of gradually decreasing conductivity adjacent to the end of the channels. Thus the electric potential gradient at the ends of the channels is reduced, and impact ionization and hot carrier effects are avoided. The effective radius of the source (or drain) junction is increased, providing increased breakdown voltage. The implantation of both phosphorus and arsenic with the resultant phosphorus peripheral band after annealing is used with self-aligned silicided source/drain regions to prevent silicide spiking through shallow arsenic regions to the P substrate and to prevent source/drain junction consumption during silicidation.

Silicided MOS transistor

The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

DRAM process with improved polysilicon-to-polysilicon capacitor and the

A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. Normally this conductive layer is stripped to avoid shorting out devices. However, the present invention patterns this conductive layer, thereby providing a local interconnect with the sheet resistance of the order of one ohm per square. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect level fulfills all of the functions which a buried contact layer could fulfill, and fulfills other functions as well.

VLSI interconnect method and structure

DRAM process with improved poly-to-poly capacitor

A CMOS process wherein lightly doped drain extensions are fabricated in the N-channel devices without any additional masking steps. The present invention requires a specific sequence of steps, after all steps through patterning of the polysilicon gate level have been completed: first, a light shallow N-type implant is performed overall. Next, oxide is deposited overall. Second, photoresist is patterned according to the P-type source/drain mask. The exposed conformal oxide is etched away completely, and the P-type source/drain implant is performed. Third, after the P-type source/drain photoresist is removed, the conformal oxide is anisotropically etched to leave sidewall oxide filaments, the N+ source/drain masking layer is applied, and the N+ source/drain implant is performed. This process results in short lightly doped drain extensions on the source/drain regions of the N-type devices only and not of the P-type devices. Alternatively, the conformal oxide is not deposited until after the pt source/drain resist is removed, so that the PMOS devices also have sidewall oxides (for better topography), but not lightly doped drain extension.

CMOS sidewall oxide-lightly doped drain process

The described embodiments of the present invention show a structure and process for fabricating this structure in which a bi-stable logic device, such as a static random access memory cell, is formed. The advantages of the described embodiments are most particularly found when in an array. In two parrallel lines formed in buried diffusions beneath the surface of the integrated circuit, V.sub.dd or the power supply voltage and ground are alternately provided. Two vertical transistors control conduction between ground and a surface diffusion are formed being connected to the buried ground diffusion. Two additional transistors are formed as load devices connected between the surface diffusion and the V.sub.dd buried diffusion. The surface diffusion is connected to complementary bit lines via access transistors formed connecting the surface diffusion to contact points for the complementary bit lines. By using buried ground and supply lines, large space savings may be obtained with the present memory cell. In addition, because of the vertical structure of all devices inthe memory cell, increased soft error immunity is obtained. Further space savings are achieved by the use of local interconnect processing for forming interconnections between surface devices in the cells. In another embodiment, a buried diffusion is used as an interconnection node for a bi-stable device using vertical devices.

Bistable logic device using trench transistors

The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

DRAM with improved poly-to-poly capacitor

The described embodiments of the present invention provide structures and methods for fabricating the structures which provide compact contact from the surface of an integrated circuit to a buried layer formed in conjunction with a vertical gate extending from the buried layer to a doped layer at a surface of the integrated circuit. In one embodiment, trenches are simultaneously formed for providing the vertical gate and the contact to the buried layer. A thermal oxide layer is formed on the surface of the integrated circuit to provide an insulating layer on the surfaces of both the contact trench and the gate trench. A first layer of in situ doped polycrystalline silicon is deposited on the surface of the integrated circuit. The thickness of this polycrystalline silicon layer is chosen so as to not fill the gate and contact trenches. A masking layer is then provided to protect the gate trench and expose the contact trench. An anisotropic etching process is then performed which removes the bottom portion of the polycrystalline silicon layer and the thus exposed portion of the gate oxide at the bottom of the contact trench. The masking layer is removed and the balance of the trenches is filled with a second in situ doped polycrystalline silicon layer which fills the gate trench to provide a high conductivity vertical gate and fills the contact trench. At the bottom of the contact trench, the second polycrystalline silicon layer is in contact with the substrate, some of the dopant atoms in the first and second polycrystalline silicon layers will diffue into the buried layer.

Process for simultaneous formation of trench contact and vertical

The disclosure relates to a CMOS flow process for formation of high and low voltage transistors simultaneously in a single semiconductor chip. The low and high voltage transistors share the same gate oxide thickness and the same polysilicon gate level. This is accomplished without any additional masking steps and through the use of a separate lightly doped drain for the high voltage N-channel devices. The sources of the high voltage N-channel devices are fabricated using the more heavily concentrated LDD implant normally used for the low voltage transistors. This minimizes the source resistance of the high voltage transistor which results in higher performance through improved saturated transconductance. From a high voltage capability point of view, the flow permits the realization of a single level polysilicon single gate oxide thickness low/high voltage CMOS process.

Dual LDD submicron CMOS process for making low and high voltage

A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealing, the source/drain regions have graded regions of gradually decreasing conductivity adjacent to the end of the channels. Thus the electric potential gradient at the ends of the channels is reduced, and impact ionization and hot carrier effects are avoided. The effective radius of the source (or drain) junction is increased, providing increased breakdown voltage.

NMOS source/drain doping with both P and As

A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.

Process for making CMOS device with both P+ and N+ gates including

Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).

Through-field implant isolated devices and method

An SRAM using TiN local interconnects. This permits the moat parasitic capacitance to be reduced, and also avoids use of metal jumpers, resulting in increased density.

SRAM with local interconnect

The present invention teaches a new method for formation of thin dielectrics over polysilicon. This technique permits the fabrication of poly-to-poly capacitors with high specific capacitance (capacitance per unit area). This technique is completely compatible with standard MOS dual poly regrown gate oxide processes. The high value of specific capacitance is achieved by using a composite dielectric which has high dielectric integrity and whose thickness is completely independent of the formation of the regular gate oxide under the second poly. No extra mask steps are required. The composite dielectric is formed as a grown or deposited oxide followed by a deposited nitride which is then reoxidized. Optionally, a second oxide is deposited before reoxidation performed.

Thin dielectrics over polysilicon

Disclosed is an integrated circuit process which includes forming two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices. The TiN gates in the second set of transistors and the TiN interconnect are formed by providing a thin film insulator pattern, depositing a titanium layer overall, heating the titanium in a nitrogen bearing atmosphere, and subsequently etching the titanium nitride obtained.

Growing community of inventors

Richardson, TX, United States of America

Roger A Haken