United Test and Assembly Center Limited

Qimonda Ag

United Test and Assembly Test Center Ltd.

Rodel Manalac

Kian Teng Eng

Pang Hup Ong

Hien Boon Tan

Wolfgang Hetzel

Werner Josef Reiss

Francis YongWee Poh

Soo Pin Chow

Jaime Siat

Roland Cordero

Florian Ammer

Denver Paul C Castillo

Yong Chuan Koh

Jimmy Siat

Bryan Soon Hua Tan

Jeffrey Nantes Salamat

Lope Vallespin Pepito, Jr

Ronaldo Cayetano Calderon

A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 kgf, the heat has a temperature range from approximately 150 to 200&#xb0; C. and the pressure is applied for a range of approximately 1 to 10 seconds.

Semiconductor package and method of attaching semiconductor dies to substrates

A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated with an OSP material. A copper wire bond electrically couples the first and second contact regions. Wire bonding includes forming a ball bump on the first contact region having a flat top surface. Providing the flat top surface is achieved with a smoothing process. A ball bond is formed on the second contact region, followed by stitching the wire onto the flat top surface of the ball bump on the first contact region.

Copper on organic solderability preservative (OSP) interconnect and enhanced wire bonding process

An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.

Integrated circuit package with leadframe enhancement and method of manufacturing the same

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Singapore, Singapore

Rodel Manalac