Freescale Semiconductor,inc.

Rode R Mora

Leo Mathew

Toni D Van Gompel

Michael D Turner

Mark Douglas Hall

Sung-Taeg Kang

Brian A Winstead

Tab Allen Stephens

Konstantin V Loiko

Dharmesh Jawarani

John R Alvis

John E Moore

Michael G Harrison

Jian Feng Chen

Bich-Yen Nguyen

Suresh Venkatesan

Robert F Steimle

Laegu Kang

Tien Ying Luo

Marc A Rossow

John J Hackenberg

Yasuhito Shiho

Anne M Vandooren

Kuang-Hsin Chen

A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer () and a dielectric layer () disposed between the substrate and the semiconductor layer, (b) creating a trench () which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure () which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer () which comprises a second material and which is disposed on the bottom of the trench.

Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner

A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region. The method further includes removing a portion of the horizontal active region, which is not covered by the sidewall spacer. The method further includes removing the sidewall spacer. The method further includes forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region. The method further includes forming a gate electrode over the gate dielectric. The method further includes forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.

Method of making an inverted-T channel transistor

A semiconductor fabrication process includes forming a gate electrode () overlying a gate dielectric () overlying a semiconductor substrate () of a wafer () and a liner dielectric layer () including vertical portions () adjacent sidewalls of the gate electrode and horizontal portions () overlying an upper surface of the semiconductor substrate (). A spacer () is formed adjacent a vertical portion () and overlying a horizontal portion () of the liner dielectric layer (). After forming the spacer (), exposed portions of the liner dielectric layer () are removed to form a liner dielectric structure () covered by the extension spacer (). The extension spacer () is then etched back to expose or uncover extremities of the liner dielectric structure (). Prior to etching back the spacer (), a metal () may be sputtered deposited over the wafer () preparatory to forming a silicide (). After the etch back the wafer () may be dipped in piranha solution and cleaned with an RF sputter () of argon.

Semiconductor fabrication process including silicide stringer removal processing

A non-volatile memory (NVM) cell comprising a layer of discrete charge storing elements, a control gate, and a select gate is provided. The control gate has a first sidewall with a lower portion being at least a first angle 10 degrees away from 90 degrees with respect to substrate. Further, the select gate has a second sidewall with a lower portion being at least a second angle at least 10 degrees away from 90 degrees with respect to the substrate. The NVM cell further comprises a layer of dielectric material located between the first sidewall and the second sidewall.

Split gate non-volatile memory cell

Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.

Semiconductor structure pattern formation

A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a part of the barrier layer and at least a part of the pad oxide layer are etched through the at least one opening resulting in a trench pad oxide layer. Etching of the trench pad oxide layer stops substantially at a top surface of the substrate within the isolation trench. An oxide layer is grown by diffusion on at least the top surface of the substrate corresponding to the at least one isolation trench. The method further includes etching the oxide layer and at least a portion of the substrate to form at least one isolation trench opening.

Method of forming a semiconductor isolation trench

Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.

Split gate memory cell method

A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.

Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer

A semiconductor fabrication process includes forming a gate electrode overlying a substrate. A first silicon nitride spacer is formed adjacent the gate electrode sidewalls and a disposable silicon nitride spacer is then formed adjacent the offset spacer. An elevated source/drain structure, defined by the boundaries of the disposable spacer, is then formed epitaxially. The disposable spacer is then removed to expose the substrate proximal to the gate electrode and a shallow implant, such as a halo or extension implant, is introduced into the exposed substrate proximal the gate electrode. A replacement spacer is formed substantially where the disposable spacer existed a source/drain implant is done to introduce a source/drain impurity distribution into the elevated source drain. The gate electrode may include an overlying silicon nitride capping layer and the first silicon nitride spacer may contact the capping layer to surround the polysilicon gate electrode in silicon nitride.

Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing

A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.

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Austin, TX, United States of America

Rode R Mora