Lsi Logic Corporation

Rochit Rajsuman

Michael J Colwell

Zarir B Sarkari

Ray Abrishami

Ching-Yen Ho

Several hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic are described. Each circuit configuration includes two registers that surround the Domino logic to allow that logic to be tested. One of the registers receives an input test vector that can either be loaded directly through a primary set of inputs or by a serial scan chain if the inputs to the register are not directly accessible. The second register is used to latch the results of the test vector application. The contents of this register can then either be read directly through a primary set of outputs if there is no static CMOS logic between the outputs of the register and a primary set of outputs of the circuit, or scanned out of the second register using a serial scan chain. A Domino scan flip-flop is also described that produces significant transistor count reduction over conventional static scan flip-flops. These Domino scan flip-flops can be used in the Domino logic as sequential elements to allow a multiplicity of logic functions to be implemented using Domino logic. These scan flip-flops can then be serially connected either as part of a separate scan chain or integrated into a single scan chain with the registers and any other static scan flip-flops in the circuit. These Domino scan flip flops allow all of the nominal logic to be tested in conjunction with the two registers. A relationship between a Domino clock that is used to drive the Domino logic in a system clock that is used to drive the static CMOS logic is described which ensures that a correct test data is applied and read out from the hybrid circuit.

Domino scan architecture and domino scan flip-flop for the testing of

An application specific integrated circuit having an embedded microprocessor and core including a memory array, self tests at full operational speed utilizing the computational power of the embedded microprocessor for deterministic testing performed by core specific test algorithms implemented in the assembly code of the embedded microprocessor.

Application specific integrated circuit chip and method of testing same

Hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic include two registers that surround the Domino logic to allow that logic to be tested. One register receives an input test vector, loaded directly through a primary set of inputs or by a serial scan chain if the register inputs are not directly accessible. The second register latches the results of the test vector application. The register contents can either be read directly through a primary set of outputs if there is no static CMOS logic between the register outputs and a primary set of circuit outputs, or scanned out of the second register using a serial scan chain. Domino scan flip-flops, which reduce transistor count over conventional static scan flip-flops, can be used in the Domino logic as sequential elements to implement multiple logic functions. These scan flip-flops can be serially connected as part of a separate scan chain or integrated into a single scan chain with the registers and any other static scan flip-flops in the circuit. Domino scan flip-flops allow all of the nominal logic to be tested in conjunction with the two registers. A Domino clock used to drive the Domino logic and a system clock used to drive the static CMOS logic ensures that correct test data is applied and read out from the hybrid circuit.

An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.

Growing community of inventors

San Jose, CA, United States of America

Rochit Rajsuman